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Vianney Lapôtre
73
Documents
Researcher identifiers
vianney-lapotre
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0000-0002-8091-0703
- Google Scholar : https://scholar.google.fr/citations?user=w0aSCHcAAAAJ&hl=fr
- IdRef : 176951911
Presentation
I received my M.Sc. and my Ph.D. in Electrical and Computer Engineering from the University Bretagne Sud, France, in 2010 and 2013 respectively. In 2012 I spent six months as an invited researcher at the Ruhr-University of Bochum, Germany. From 2013 to 2014, I was a Postdoctoral at LIRMM, Montpellier, France. I was involved in the European Mont-Blanc project. I am currently associate professor at University Bretagne Sud, France. My research interests include hardware security, embedded processors and reconfigurable hardware architectures.
I received my M.Sc. and my Ph.D. in Electrical and Computer Engineering from the University Bretagne Sud, France, in 2010 and 2013 respectively. In 2012 I spent six months as an invited researcher at the Ruhr-University of Bochum, Germany. From 2013 to 2014, I was a Postdoctoral at LIRMM, Montpellier, France. I was involved in the European Mont-Blanc project. I am currently associate professor at University Bretagne Sud, France. My research interests include hardware security, embedded processors and reconfigurable hardware architectures.
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On The Effect of Replacement Policies on The Security of Randomized Cache Architectures19th ACM ASIA Conference on Computer and Communications Security (ACM ASIACCS 2024), Jul 2024, Singapore, Singapore. pp.483-497, ⟨10.1145/3634737.3637677⟩
Conference papers
hal-04427321v1
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Verrouillage des lignes de cache pour la lutte contre les attaques par canaux auxiliaires exploitant les mémoires cachesCyber On Board, Mar 2024, ile des Embiez, France
Conference papers
hal-04461273v1
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Defending the Citadel: Fault Injection Attacks against Dynamic Information Flow Tracking and Related Countermeasures2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Jul 2024, Knoxville, United States
Conference papers
hal-04620057v1
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Communication Architecture Under Siege: An In-depth Analysis of Fault Attack Vulnerabilities and CountermeasuresIEEE CSR Workshop on Hardware Cybersecurity Systems (HACS), Sep 2024, London, United Kingdom
Conference papers
hal-04691839v1
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Scripting the Unpredictable: Automate Fault Injection in RTL Simulation for Vulnerability Assessment27th Euromicro Conference Series on Digital System Design (DSD), Sorbonne University, Aug 2024, Paris, France
Conference papers
hal-04683084v1
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Exploring Fault Injection Attacks on CVA6 PMP Configuration Flow27th Euromicro Conference Series on Digital System Design (DSD), Sorbonne University, Aug 2024, Paris, France
Conference papers
hal-04683083v1
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A Fine-Grained Dynamic Partitioning Against Cache-Based Timing Attacks via Cache Locking2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2024), Jul 2024, Knoxville, TN, United States
Conference papers
hal-04619896v1
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Cache locking against cache-based side-channel attacksÉcole d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes (FETCH), Université Libre de Bruxelles, Feb 2024, Maillen, Belgium
Conference papers
hal-04446221v1
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Another Break in the Wall: Harnessing Fault Injection Attacks to Penetrate Software FortressesSensorsS&P: First International Workshop on Security and Privacy of Sensing Systems, Nov 2023, Istanbul Turkiye, France. pp.8-14, ⟨10.1145/3628356.3630116⟩
Conference papers
hal-04286507v1
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Protecting a RISC-V embedded processor against physical and software attacksBITFLIP by DGA - European Cyber Week 2023, Nov 2023, Rennes, France
Conference papers
hal-04381708v1
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Work in Progress: Thwarting Timing Attacks in Microcontrollers using Fine-grained Hardware Protections2023 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW), Jul 2023, Delft, Netherlands. pp.1-7
Conference papers
hal-04155139v1
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When in-core DIFT faces fault injection attacksCryptArchi 2023 - 19th International Workshops on Cryptographic architectures embedded in logic devices, Jun 2023, Cantabria, Spain
Conference papers
hal-04381235v1
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Processor Extensions for Hardware Instruction Replay against Fault Injection AttacksDDECS: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2022, Prague, Czech Republic
Conference papers
hal-03599317v1
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Toward Secured IoT Devices: a Shuffled 8-Bit AES Hardware ImplementationIEEE International Symposium on Circuits and Systems (ISCAS), Oct 2020, Seville, Spain. ⟨10.1109/ISCAS45731.2020.9180599⟩
Conference papers
hal-02511667v1
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Sherlock Holmes of Cache Side-Channel Attacks in Intel's x86 ArchitectureIEEE-Communications and Network Security, Jun 2019, Washington DC, United States
Conference papers
hal-02151838v1
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A hardware/software co-design approach for security analysis of application behaviorJournée "Nouvelles Avancées en Sécurité des Systèmes d'Information, INSA de Toulouse; LAAS-CNRS, Jan 2019, Toulouse, France
Conference papers
hal-02013870v1
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Fast Evaluation of Homomorphic Encryption Schemes Based on Ring-LWE2018 9th IFIP International Conference on New Technologies, Mobility and Security (NTMS), Feb 2018, Paris, France. ⟨10.1109/NTMS.2018.8328693⟩
Conference papers
hal-01757093v1
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Machine Learning For Security: The Case of Side-Channel Attack Detection at Run-timeICECS-2018, Dec 2018, Bordeaux, France
Conference papers
hal-01876792v1
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A small and adaptive coprocessor for information flow tracking in ARM SoCsReConFig 2018 - International Conference on Reconfigurable Computing and FPGAs, Dec 2018, Cancun, Mexico. pp.1-17, ⟨10.1109/reconfig.2018.8641695⟩
Conference papers
hal-01911619v1
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A novel lightweight hardware-assisted static instrumentation approach for ARM SoC using debug componentsAsianHOST 2018 - Asian Hardware Oriented Security and Trust Symposium, Dec 2018, Hong Kong, China. pp.1-13, ⟨10.1109/asianhost.2018.8607177⟩
Conference papers
hal-01911621v1
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Run-time Detection of Prime+Probe Side-Channel Attack on AES Encryption AlgorithmGlobal Information Infrastructure and Networking Symposium (GIIS), Oct 2018, Thessaloniki, Greece
Conference papers
hal-01879950v1
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NIGHTs-WATCH: A Cache-based Side-channel Intrusion Detector Using Hardware Performance Counters7th International Workshop on Hardware and Architectural Support for Security and Privacy, Jun 2018, Los Angeles, United States. ⟨10.1145/3214292.3214293⟩
Conference papers
hal-01806729v1
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Cache-Based Side-Channel Intrusion Detection using Hardware Performance CountersCryptArchi 2018 - 16th International Workshops on Cryptographic architectures embedded in logic devices, Jun 2018, Lorient, France
Conference papers
cel-01824512v1
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ARMHEx: A hardware extension for DIFT on ARM-based SoCs2017 27th International Conference on Field Programmable Logic and Applications (FPL), Sep 2017, Ghent, Belgium. ⟨10.23919/fpl.2017.8056767⟩
Conference papers
hal-01558473v1
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Using a Virtual Plant to Support the Development of Intelligent Gateway for Sensors/Actuators SecurityIFAC World Congress, Jul 2017, Toulouse, France. pp.5837-5842
Conference papers
hal-01961897v1
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ARMHEx: embedded security through hardware-enhanced information flow trackingRESSI 2017 : Rendez-vous de la Recherche et de l'Enseignement de la Sécurité des Systèmes d'Information, May 2017, Grenoble (Autrans), France
Conference papers
hal-01558155v1
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Improving Confidentiality Against Cache-based SCAsACM WomENcourage, Sep 2017, barcelona, France
Conference papers
hal-01748057v1
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PAnTHErS: A Prototyping and Analysis Tool for Homomorphic Encryption SchemesSECRYPT: 14th International Conference on Security and Cryptography, Jul 2017, Madrid, Spain
Conference papers
hal-01595789v1
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Somewhat/Fully Homomorphic Encryption: Implementation Progresses and ChallengesC2SI 2017 : 2nd International Conference on Codes, Cryptology and Information Security, Apr 2017, Rabat, Morocco. pp.68 - 82, ⟨10.1007/978-3-319-55589-8_5⟩
Conference papers
hal-01596540v1
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ALMOS many-core operating system extension with new secure-enable mechanisms for dynamic creation of secure zones24th Euromicro International Conference on Parallel, Distributed and Netwprk-Based Processing (PDP 2016), Feb 2016, Heraklion - Crete, Greece
Conference papers
hal-01273173v1
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MPSoCSim extension: An OVP Simulator for the Evaluation of Cluster-based Multicore and Many-core architectures4rd Workshop on Virtual Prototyping of Parallel and Embedded Systems (ViPES) as part of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Jul 2016, Samos, Greece
Conference papers
hal-01347188v1
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Towards a hardware-assisted information flow tracking ecosystem for ARM processors26th International Conference on Field-Programmable Logic and Applications (FPL 2016), Aug 2016, Lausanne, Switzerland. ⟨10.1109/fpl.2016.7577396⟩
Conference papers
hal-01337579v1
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Dynamic Spatially Isolated Secure Zones for NoC-based Many-core Accelerators8th IEEE International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Jun 2016, Tallinn, Estonia. ⟨10.1109/ReCoSoC.2016.7533900⟩
Conference papers
hal-01347175v1
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Fast polynomial arithmetic for Somewhat Homomorphic Encryption operations in hardware with Karatsuba algorithmInternational Conference on Field-Programmable Technology (FPT), Dec 2016, Xi’an, China. ⟨10.1109/FPT.2016.7929535⟩
Conference papers
hal-01427642v1
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A portable approach for SoC-based Dynamic Information Flow Tracking implementations11ème Colloque du GDR SoC/SiP, Jun 2016, Nantes, France
Conference papers
hal-01311045v1
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Exploration of Polynomial Multiplication Algorithms for Homomorphic Encryption SchemesInternational Conference on Reconfigurable Computing and FPGAs (ReConFig), Dec 2015, Cancun, Mexico. ⟨10.1109/ReConFig.2015.7393307⟩
Conference papers
hal-01273192v1
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A trace-driven approach for fast and accurate simulation of manycore architecturesASP-DAC: Asia and South Pacific Design Automation Conference, Jan 2015, Chiba, Tokyo, Japan. pp.707-712, ⟨10.1109/ASPDAC.2015.7059093⟩
Conference papers
lirmm-01255921v1
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On the Performance Exploration of 3D NoCs with Resistive-Open TSVsISVLSI 2015 - International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.579-584, ⟨10.1109/ISVLSI.2015.49⟩
Conference papers
lirmm-01248588v1
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Performance exploration of partially connected 3D NoCs under manufacturing variabilityNEWCAS 2014 - 12th IEEE International New Circuits and Systems Conference, Jun 2014, Trois-Rivieres, QC, Canada. pp.61-64, ⟨10.1109/NEWCAS.2014.6933985⟩
Conference papers
lirmm-01248595v1
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Optimizations for an efficient reconfiguration of an ASIP-based turbo decoderISCAS 2013 : IEEE International Symposium on Circuits and Systems, May 2013, Beijing, Chine. pp.493 - 496, ⟨10.1109/ISCAS.2013.6571888⟩
Conference papers
hal-00873979v1
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Plateforme multi-ASIP reconfigurable dynamiquement pour le turbo décodage dans un contexte multi-standardGRETSI 2013 : 24ème colloque du Groupement de Recherche en Traitement du Signal et des Images, Sep 2013, Brest, France
Conference papers
hal-00876009v1
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Rapid Design and Prototyping of a Reconfigurable Decoder Architecture for QC-LDPC CodesRSP 2013 : 24th IEEE International Symposium on Rapid System Prototyping, Oct 2013, Montreal, Canada
Conference papers
hal-00876088v1
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An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architectureReCoSoC 2013 : 8th IEEE International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Jul 2013, Darmstadt, Germany. ⟨10.1109/ReCoSoC.2013.6581518⟩
Conference papers
hal-00873978v1
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Dynamic Branch Prediction For High-Level SynthesisInternational Conference on Field Programmable Logic and Applications, Sep 2013, Portugal. pp.XX-YY
Conference papers
hal-00830417v1
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Stopping-free dynamic configuration of a multi-ASIP turbo decoderDSD 2013 : 16th Euromicro Conference on Digital System Design, Sep 2013, Santander, Spain. pp.155 - 162
Conference papers
hal-00876005v1
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A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIPISVLSI 2013 : IEEE Computer Society Annual Symposium on VLSI, Aug 2013, Natal, Brazil. ⟨10.1109/ISVLSI.2013.6654620⟩
Conference papers
hal-01002828v1
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An analytical approach for sizing of heterogeneous multiprocessor flexible platform for iterative demapping and channel decodingInternational Conference on ReConFigurable Computing and FPGAs (Reconfig), Dec 2012, Cancun, Mexico. ⟨10.1109/ReConFig.2012.6416728⟩
Conference papers
hal-00747714v1
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Prédiction de Branchement dans la Synthèse de Haut NiveauSYMPosium en Architectures, Saint Malo, Mai 2011, May 2011, St Malo, France. pp.XX-YY
Conference papers
hal-00592606v1
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Management of reconfigurable multi-standards ASIP-based receiverSOC-SIP : colloque national du groupe de recherches System On Chip - System In Package, Jun 2011, Lyon, France
Conference papers
hal-00724998v1
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Exploring Fault Injection Attacks on CVA6 PMP Configuration FlowJournée thématique sur les attaques par injection de fautes (JAIF), Oct 2024, Rennes, France
Conference poster
hal-04729617v1
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Characterizing Clock Glitching Attacks on CVA6 PMP Configuration FlowCYBERUS Spring School 2024, Apr 2024, Lorient, France
Conference poster
hal-04729593v1
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Unveiling the Invisible Threads: Dynamic Information Flow Tracking and the Intriguing World of Fault Injection AttacksConference poster hal-04727439v1 |
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When in-core DIFT faces fault injection attacksRISC-V Summit Europe 2023,, Jun 2023, Barcelone, Spain. 2023
Conference poster
hal-04132319v1
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Protection of a processor with DIFT against physical attacksInternational Winter School on Microarchitectural Security, Dec 2022, Paris, France. 2022
Conference poster
hal-04727408v1
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ARMHEx: a framework for efficient DIFT in real-world SoCsConference poster hal-01558475v1 |
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HardBlare: a Hardware-Assisted Approach for Dynamic Information Flow TrackingSéminaire des doctorantes et doctorants en informatique de la Société Informatique de France, Apr 2016, Paris, France. 2016
Conference poster
hal-01311032v1
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HardBlare: an efficient hardware-assisted DIFC for non-modified embedded processorsCHES 2015 - Workshop on Cryptographic Hardware and Embedded Systems, Sep 2015, Saint-Malo, France. 2015
Conference poster
hal-01252597v1
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Multithreading for Compute Accelerators Through Distributed Shared Memory DesignDAC: Design Automation Conference, Jun 2014, San Francisco, United States. IEEE Design Automation Conference, 2014, Work-in-Progress Session
Conference poster
lirmm-01419120v1
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Efficient dynamic configuration of a multi-ASIP turbo decoderGDR SoC-SiP 2013 : Colloque National du Groupe de Recherche System on Chip -System in Package, Jun 2013, Lyon, France
Conference poster
hal-00876017v1
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Toward dynamically reconfigurable high throughput multiprocessor Turbo decoder in a multimode and multi-standard contextElectronics. Université de Bretagne-Sud, 2013. English. ⟨NNT : ⟩
Theses
tel-01096975v1
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Contributions à la sécurité des systèmes embarqués face aux attaques logiques et physiquesArchitectures Matérielles [cs.AR]. Université Bretagne Sud, 2023
Accreditation to supervise research
tel-04155274v1
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