Yann Kieffer
Publications
Publications
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Beyond FAP: ANTXR1 as a novel target for PET imaging and radio-ligand therapy in immuno-oncology?European Journal of Nuclear Medicine and Molecular Imaging, 2025, 52 (6), pp.1948-1950. ⟨10.1007/s00259-025-07126-0⟩ |
Proposal of a lightweight differential power analysis countermeasure method on elliptic curves for low-cost devicesMultimedia Tools and Applications, 2024, 83 (30), pp.74657-74683. ⟨10.1007/s11042-024-18368-9⟩ |
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Minimizing makespan under data prefetching constraints for embedded vision systems: a study of optimization methods and their performanceOperational Research, 2021, ⟨10.1007/s12351-021-00647-0⟩ |
Embedded Elapsed Time Techniques in Trusted Execution Environment for Lightweight Blockchain2024 IEEE International Conference on Blockchain (Blockchain), Aug 2024, Copenhagen, Denmark. pp.81-88, ⟨10.1109/Blockchain62396.2024.00020⟩ |
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Securing Elapsed Time for Blockchain: Proof of Hardware Time and Some of its Physical Threats2024 27th Euromicro Conference on Digital System Design (DSD), Aug 2024, Paris, France. pp.137-144, ⟨10.1109/DSD64264.2024.00027⟩ |
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Secure-by-Design Methodology using Meet-in-the-Middle Design Flow for Hardware Implementations of ECC-based Passive RFID TagsConference: International Conference on Wireless and Mobile Communications, Mar 2023, Barcelona, Spain |
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Low-cost Low-Power Implementation of Binary Edwards Curve for Secure Passive RFID Tags2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Dec 2023, Singapore, Singapore. pp.494-500, ⟨10.1109/MCSoC60832.2023.00079⟩ |
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Preuve vérifiable pour une blockchain embarquée basse consommationColloque du GDR SoC², Jun 2023, Lyon, France |
Adoption of a Secure ECC-based RFID Authentication Protocol2022 IEEE 9th International Conference on Sciences of Electronics, Technologies of Information and Telecommunications (SETIT), May 2022, Hammamet, Tunisia. pp.69-74, ⟨10.1109/SETIT54465.2022.9875855⟩ |
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Hardware Implementation of Secure scalar multiplication Algorithm2022 IEEE 9th International Conference on Sciences of Electronics, Technologies of Information and Telecommunications (SETIT), May 2022, Hammamet, Tunisia. pp.81-86, ⟨10.1109/SETIT54465.2022.9875647⟩ |
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An Experimental Study on Symmetry Breaking Constraints Impact for the One Dimensional Bin-Packing Problem13th International Workshop on Computational Optimization (Fedcsis-WCO 2020), Sep 2020, Sofia, Bulgaria. pp.317-326, ⟨10.15439/2020f19⟩ |
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Nouvelle formulation en PLNE pour le problème classique du Bin PackingCongrès Annuel de la Société Française de Recherche Opérationnelle et Aide à la Décision (ROADEF 2019), Feb 2019, Le Havre, France |
Minimisation du temps total de traitement pour optimiser le fonctionnement d’un contrôleur de buffers pour les systèmes de vision embarquée18ème édition du congrès annuel de la Société Française de Recherche Opérationnelle et d'Aide à la Décision (ROADEF 2017), Feb 2017, Metz, France |
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Multi-objective optimization for the scheduling of embedded vision acceleratorsThe 29th Conference of the European Chapter on Combinatorial Optimization (ECCO'16), May 2016, Budapest, Hungary |
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Memory Management in Embedded Vision Systems: Optimization Problems and Solution MethodsThe Conference on Design, Architectures for Signal and Image Processing (DASIP'16), Oct 2016, Rennes, France |
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Minimisation des accès mémoires dans un cache intelligent pour les systèmes de vision embarquée17ème Congrès Annuel de la Société Française de Recherche Opérationnelle et Aide à la Décision, Feb 2016, Compiègne, France. pp.1-2 |
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Optimisation du Fonctionnement d’un Contrôleur de Buffers pour les Systèmes de Vision EmbarquéeConférence d’informatique en Parallélisme, Architecture et Système (ComPAS'16), Jul 2016, Lorient, France |
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Efficient Algorithms for Memory Management in Embedded Vision SystemsThe 11th IEEE International Symposium on Industrial Embedded Systems (SIES-WIP'16), May 2016, Krakow, Poland |
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Formulation and Practical Solution for the Optimization of Memory Accesses in Embedded Vision SystemsThe 9th International Workshop on Computational Optimization (WCO'16), Sep 2016, Gdansk, Poland |
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Minimizing Test Frequencies for Linear Analog Circuits: New Models and Efficient Solution Methods21th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2013, Istanbul, Turkey. pp.188-207, ⟨10.1007/978-3-319-23799-2_9⟩ |
Efficient minimization of test frequencies for linear analog circuits18th IEEE European Test Symposium (ETS), May 2013, Avignon, France |
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New techniques for selecting test frequencies for linear analog circuitsInternational Conference on Very Large Scale Integration (VLSI-SoC), Oct 2013, Istamboul, Turkey |
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A global optimization for scan chain insertion at the RT-levelIEEE Annual Symposium on VLSI 2011, Jul 2011, Chennai, India. pp.321-322, ⟨10.1109/ISVLSI.2011.46⟩ |
Modification d'instances : Pourquoi et comment ?ROADEF 2011, 12e congrès annuel de la Société française de Recherche Opérationnelle et d'Aide à la Décision, Mar 2011, Saint-Etienne, France. A paraître |
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A multi-objective optimization for memory BIST sharing using a genetic algorithmIEEE International On-Line Testing Symposium, Jul 2011, Athens, Greece. pp.73-78, ⟨10.1109/IOLTS.2011.5993814⟩ |
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Etude d'instances pour les problèmes NP-difficilesJGA - 13èmes Journées Graphes et Algorithmes 2011, Nov 2011, Lyon, France |
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A Complete methodology for determining memory BIST optimization under wrappers sharing constraints.Asia Symposium on Quality Electronic Design, Jul 2011, Kuala Lumpur, Malaysia. pp.46-53, ⟨10.1109/ASQED.2011.6111701⟩ |
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Nouvelles classes d'instances non-métriques pour le TSP11ème Congrès de la Société Française de Recherche Opérationnelle et d'Aide à la Décision, Feb 2010, Toulouse, France |
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Optimisation du partage de blocs BIST pour le test des mémoires d'un circuit intégré11e Congrès annuel de la société française de Recherche Opérationnelle et d'Aide à la Décision ROADEF 2010, Feb 2010, Toulouse, France |
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A solution to optimize shared Memory Bist systemDesign Automation and Test in Europe Conference, Mar 2010, Dresden, Germany. pp.130 |
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A Shared BIST Optimization Methodology for Memory Test15th IEEE European Test Symposium, May 2010, Prague, Czech Republic. p255 |
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Multi-objective optimization of Memory Built-In-Self-Test sharing24rd EURO European Conference On Operational Resarch, Jul 2010, Lisbon, Portugal |
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Optimization for the test of on-chip memoriesInternational Symposium on Combinatorial Optimization, Mar 2010, Hammamet, Tunisia |
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Optimizing memory BIST systems under sharing constraintsCOLLOQUE NATIONAL DU GDR SOC-SIP, Jun 2010, Paris, France |
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Challenging instances for discrete optimization problems24th European Conference on Operational Resarch, Jul 2010, Lisbon, Portugal |
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A Practical Scan OptimizationAlgorithm at the Register Transfer LevelDesign Automation and Test in Europe., 2009, Nice, France. pp.22 |
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A model for Scan Insertion at The Register Transfert LevelThe Tenth IEEE Workshop on RTL and High Level Testing, Nov 2009, Hong Kong, Hong Kong SAR China. pp.185 |
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Automatizing the sharing of Bist blocks for low power testing of embedded-memories23rd EURO European Conference On Operational Resarch, 2009, Bonn, Germany |
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Une méthode pour insérer le scan au niveau RTL en une seule passeColloque national du Groupe de recherche System on Chip, System on Package, Jun 2009, Paris, France |
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Chaînage des sommets d'un graphes pour le test des circuits intégrésRoadef 2009, 10éme congrès de la société Française de Recherche Opérationnelle et d'Aide à la Désicion., 2009, Nancy, France |
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Scan chain optimization for integrated circuits testing: an operations research perspective23rd European conference on operational Research, 2009, Bonn, Germany |
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Algorithmes des chaînage des éléments mémoires d'un circuit intégréJournées Graphes et Algorithmes, 2008, --, France |
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Modélisation et optimisation d'une méthode de test d'un circuit intégréRoadef 2008, 9éme congrès de la société Française de Recherche Opérationnelle et d'Aide à la Désicion., 2008, --, France |
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Introducing the COMP projectSmall TYPES workshop: Constructive analysis, types and exact real numbers., Oct 2005, Nijmegen, Netherlands |
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Génération par ordinateur de couples de matrices partitionablesROADEF, Feb 2003, France |
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How to Develop ECC-Based Low Cost RFID Tags Robust Against Side-Channel AttacksIndustrial Networks and Intelligent Systems, 379, Springer International Publishing, pp.433-447, 2021, Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, ⟨10.1007/978-3-030-77424-0_35⟩ |
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New Symmetry-less ILP Formulation for the Classical One Dimensional Bin-Packing ProblemDonghyun Kim; R. N. Uma; Zhipeng Cai; Dong Hoon Lee. Computing and Combinatorics. 26th International Conference, COCOON 2020, Atlanta, GA, USA, August 29–31, 2020, Proceedings, 12273, Springer, pp.423-434, 2020, Lecture Notes in Computer Science, 978-3-030-58149-7. ⟨10.1007/978-3-030-58150-3_34⟩ |
Meeting the Challenges of Optimized Memory Management in Embedded Vision Systems Using Operations ResearchRecent Advances in Computational Optimization, springer pp.177-205, 2018 |
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Applying Operations Research to Design for Test Insertion ProblemsComputational Intelligence in Digital and Network Designs and Applications, 2015, ⟨10.1007/978-3-319-20071-2_6⟩ |
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Minimizing test frequencies for linear analog circuits: new models and efficient solution methodsin VLSI-SoC: At the Crossroads of Emerging Trends, springer pp.188-207, 2015, 978-3-319-23799-2. ⟨10.1007/978-3-319-23799-29⟩ |
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New optimization techniques for selecting test frequencies for linear analog circuitsIFIP VLSI SoC SIP, 2015 |
Toward an Optimal Scan Insertion at the Register Transfer Level2010 |