Yves Mathieu
Publications
Publications
Optimized Co-Design of Delta Sigma Modulators and Fir-DACs for High Speed Transmitters2025 23rd IEEE Interregional NEWCAS Conference (NEWCAS), Jun 2025, Paris, France. pp.246-250, ⟨10.1109/NewCAS64648.2025.11107152⟩ |
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Jitter Compensation Mechanism for Dynamic Deterministic NetworksOptical Fiber Communication Conference (OFC) 2023, Mar 2023, San Diego California, United States. pp.Th3D.2, ⟨10.1364/OFC.2023.Th3D.2⟩ |
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Formal Evaluation and Construction of Glitch-resistant Masked FunctionsIEEE International Symposium on Hardware Oriented Security and Trust, HOST 2021, Dec 2021, Virtual, United States |
Detection of Side-channel Lleakage Through Glitches Using an Automated ToolInternational Conference on Defense Systems: Architectures and Technologies (DAT’2020), Apr 2020, Constantine, Algeria |
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Cache-Timing Attacks Still Threaten IoT Devices3rd International Conference on Codes, Cryptology, and Information Security (C2SI 2019), Apr 2019, Rabat, Morocco. pp.13-30, ⟨10.1007/978-3-030-16458-4_2⟩ |
Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology2018 21st Euromicro Conference on Digital System Design (DSD), Aug 2018, Prague, Czech Republic. pp.508-515 |
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Pre-Silicon Embedded System Evaluation as new EDA for Security VerificationInternational Verification and Security Workshop (IVSW), Jun 2018, Platja d’Aro, Spain |
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A 2.5ns-Latency 0.39pJ/b 289µm2/Gb/s Ultra-Light-Weight PRINCE Cryptographic ProcessorSymposium on VLSI Circuits, Jun 2017, Kyoto, Japan. pp.C266-C267 |
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IC variability : Pros and cons for security blocksTRUDEVICE, Mar 2015, Grenoble, France |
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Countering Early Propagation and Routing Imbalance of DPLInternational Conference on IC Design and Technology (ICICDT), Jun 2015, Leuven, Belgium. ⟨10.1109/ICICDT.2015.7165897⟩ |
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Cryptographically secure shieldsHOST 2014 - IEEE International Symposium on Hardware-Oriented Security and Trust, May 2014, Washington, United States. pp.25 - 31, ⟨10.1109/HST.2014.6855563⟩ |
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation MethodologyES4CPS, Mar 2014, Dresden, Germany. ⟨10.1145/2559627.2559628⟩ |
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Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical securityFPL 2014 - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. pp.1--4, ⟨10.1109/FPL.2014.6927422⟩ |
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Evaluation of delay PUFs on CMOS 65nm technology: ASIC vs FPGAInternational Workshop on Hardware and Architectural Support for Security and Privacy, HASP 2013, Jun 2013, Tel-Aviv, Israel. pp.Article n° 4 |
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Design Methodology of an ASIC TRNG based on an open-loop delay chainNEWCAS, Jun 2013, Paris, France. ⟨10.1109/NEWCAS.2013.6573654⟩ |
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A Dual Threshold Voltage Technique for Glitch Minimization19th IEEE International Conference on Electronics, Circuits and Systems, Dec 2012, Séville, Spain. pp.444-447, ⟨10.1109/ICECS.2012.6463554⟩ |
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Calibrating a predictive cache emulator for SoC designNASA/ESA Conference on Adaptive Hardware and Systems (AHS), Jun 2010, Anaheim, Californie, United States. pp.273-280, ⟨10.1109/AHS.2010.5546246⟩ |
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Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints.Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09., Apr 2009, NICE, France. pp.640-645 |
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Efficient data access management for FPGA-Based image processing SoCsRSP 2009 - 20th IEEE/IFIP International Symposium on Rapid System Prototyping, Jun 2009, Paris, France. pp.159-165 |
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High Efficiency Reconfigurable Cache for Image ProcessingERSA 2009 - 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, Jul 2009, Las Vegas USA, United States. pp.226-232 |
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Combined SCA and DFA Countermeasures Integrable in a FPGA Design FlowReConFig, Dec 2009, Cancún, Mexico. pp.213 - 218, ⟨10.1109/ReConFig.2009.50⟩ |
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Security Evaluation of a Balanced Quasi-Delay Insensitive Library (SecLib)Conference on Design of Circuits and Integrated Systems, Nov 2008, Grenoble, France. 6 p., ISBN: 978-2-84813-124-5 |
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Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAsSecure System Integration and Reliability Improvement, Jul 2008, Yokohama, Japan. pp.16-23, ⟨10.1109/SSIRI.2008.31⟩ |
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The “Backend Duplication” MethodWorkshop on Cryptographic Hardware and Embedded Systems (CHES), Aug 2005, Edinburgh, United Kingdom. pp.383-397, ⟨10.1007/11545262_28⟩ |
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Post-layout Security Evaluation Methodology Against Probing AttacksNguyen-Son Vo; Van-Phuc Hoang; Quoc-Tuan Vien. Industrial Networks and Intelligent Systems. 7th EAI International Conference, INISCOM 2021, Hanoi, Vietnam, April 22-23, 2021, Proceedings, 379, Springer International Publishing, pp.465-482, 2021, Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, 978-3-030-77423-3. ⟨10.1007/978-3-030-77424-0_37⟩ |
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Fault Analysis Assisted by SimulationJakub Breier; Xiaolu Hou; Shivam Bhasin. Automated Methods in Cryptographic Fault Analysis, Springer International Publishing, pp.263-277, 2019, 978-3-030-11332-2. ⟨10.1007/978-3-030-11333-9_12⟩ |
23 : Graphics Composition for Multiview DisplaysEmerging Technologies for 3D Video, Wiley, 2013, ⟨10.1002/9781118583593⟩ |
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Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology2019 |
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Successful Attack on an FPGA-based Automatically Placed and Routed WDDL+ Crypto Processor.2008 |
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ElectroMagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack of a Cryptographic Module2008 |