Yves Mathieu

Documents

Publications

A High-Speed Digital Delta-Sigma Modulator Based on Temporal Unrolling and Zero-Padding

Evelyn Lima , Yves Mathieu , Chadi Jabbour

IEEE Transactions on Circuits and Systems II: Express Briefs, 2026, pp.1-1. ⟨10.1109/TCSII.2026.3733779⟩

Article dans une revue hal-05770122v1

Diffusional Side-channel Leakage from Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE

Ville Yli-Mayry , Rei Ueno , Noriyuki Miura , Makoto Nagata , Shivam Bhasin et al.

IEEE Transactions on Information Forensics and Security, 2020, pp.1-1. ⟨10.1109/TIFS.2020.3033441⟩

Article dans une revue hal-02977542v1

High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

Rei Ueno , Naofumi Homma , Sumio Morioka , Noriyuki Miura , Kohei Matsuda et al.

IEEE Transactions on Computers, 2020, 69 (4), pp.534-548. ⟨10.1109/TC.2019.2957355⟩

Article dans une revue hal-02517649v1

Cryptographically Secure Shield for Security IPs Protection

Xuan-Thuy Ngo , Jean-Luc Danger , Sylvain Guilley , Tarik Graba , Yves Mathieu et al.

IEEE Transactions on Computers, 2017, 66 (2), ⟨10.1109/TC.2016.2584041⟩

Article dans une revue hal-02287686v1

Improving molecular diagnosis of distal myopathies by targeted next-generation sequencing

Amandine Sevy , Mathieu Cerino , Svetlana Gorokhova , Eugénie Dionnet , Yves Mathieu et al.

Journal of Neurology, Neurosurgery and Psychiatry, 2016, 87 (3), pp.340-U116. ⟨10.1136/jnnp-2014-309663⟩

Article dans une revue hal-01469052v1

Exploration of 3D grid caching strategies for ray-shooting

Stéphane Mancini , Zahir Larabi , Yves Mathieu , Tomasz Toczek , Lionel Pierrefeu

Journal of Real-Time Image Processing, 2012, 7 (1), pp.3-19. ⟨10.1007/s11554-010-0176-3⟩

Article dans une revue istex hal-00764379v1

Mutational, functional, and expression studies of the TCF4 gene in Pitt-Hopkins syndrome

Loic de Pontual , Yves Mathieu , Christelle Golzio , Marlène Rio , Valérie Malan et al.

Human Mutation, 2009, 30 (4), pp.669-676. ⟨10.1002/humu.20935⟩

Article dans une revue istex hal-02134020v1

Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors

Sylvain Guilley , Florent Flament , Philippe Hoogvorst , Renaud Pacalet , Yves Mathieu

IEEE Design & Test of Computers, 2007, 24 (6), pp.546-555. ⟨10.1109/MDT.2007.202⟩

Article dans une revue hal-02893104v1

Optimized Co-Design of Delta Sigma Modulators and Fir-DACs for High Speed Transmitters

Evelyn Lima , Nicolas Schlegel , Yves Mathieu , Chadi Jabbour

2025 23rd IEEE Interregional NEWCAS Conference (NEWCAS), Jun 2025, Paris, France. pp.246-250, ⟨10.1109/NewCAS64648.2025.11107152⟩

Communication dans un congrès hal-05213780v1

Jitter Compensation Mechanism for Dynamic Deterministic Networks

Guillaume Soudais , Tarik Graba , Yves Mathieu , Sebastien Bigo

Optical Fiber Communication Conference (OFC) 2023, Mar 2023, San Diego California, United States. pp.Th3D.2, ⟨10.1364/OFC.2023.Th3D.2⟩

Communication dans un congrès hal-04426205v1

Formal Evaluation and Construction of Glitch-resistant Masked Functions

Sofiane Takarabt , Sylvain Guilley , Youssef Souissi , Khaled Karray , Laurent Sauvage et al.

IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2021, Dec 2021, Virtual, United States

Communication dans un congrès hal-03365025v1

Detection of Side-channel Lleakage Through Glitches Using an Automated Tool

Laurent Sauvage , Sofiane Takarabt , Youssef Souissi , Sylvain Guilley , Yves Mathieu

International Conference on Defense Systems: Architectures and Technologies (DAT’2020), Apr 2020, Constantine, Algeria

Communication dans un congrès hal-02951758v1

Cache-Timing Attacks Still Threaten IoT Devices

Sofiane Takarabt , Alexander Schaub , Adrien Facon , Sylvain Guilley , Laurent Sauvage et al.

3rd International Conference on Codes, Cryptology, and Information Security (C2SI 2019), Apr 2019, Rabat, Morocco. pp.13-30, ⟨10.1007/978-3-030-16458-4_2⟩

Communication dans un congrès hal-02319488v1

Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology

Jean-Luc Danger , Risa Yashiro , Tarik Graba , Yves Mathieu , Abdelmalek Si-Merabet et al.

2018 21st Euromicro Conference on Digital System Design (DSD), Aug 2018, Prague, Czech Republic. pp.508-515

Communication dans un congrès hal-02271687v1

Pre-Silicon Embedded System Evaluation as new EDA for Security Verification

Sofiane Takarabt , Kais Chibani , Youssef Souissi , Laurent Sauvage , Sylvain Guilley et al.

International Verification and Security Workshop (IVSW), Jun 2018, Platja d’Aro, Spain

Communication dans un congrès hal-02287930v1

A 2.5ns-Latency 0.39pJ/b 289µm2/Gb/s Ultra-Light-Weight PRINCE Cryptographic Processor

Noriyuki Miura , Kohei Matsuda , Karol Myszkowski , Makoto Nagata , Shivam Bhasin et al.

Symposium on VLSI Circuits, Jun 2017, Kyoto, Japan. pp.C266-C267, ⟨10.23919/VLSIC.2017.8008502⟩

Communication dans un congrès hal-02288491v1

IC variability : Pros and cons for security blocks

Jean-Luc Danger , Yves Mathieu , Thibault Porteboeuf

TRUDEVICE, Mar 2015, Grenoble, France

Communication dans un congrès hal-02412162v1

Countering Early Propagation and Routing Imbalance of DPL

Emna Amouri , Shivam Bhasin , Yves Mathieu , Tarik Graba , Jean-Luc Danger

International Conference on IC Design and Technology (ICICDT), Jun 2015, Leuven, Belgium. ⟨10.1109/ICICDT.2015.7165897⟩

Communication dans un congrès hal-02287122v1

Cryptographically secure shields

Jean-Michel Cioranesco , Jean-Luc Danger , Tarik Graba , Sylvain Guilley , Yves Mathieu et al.

HOST 2014 - IEEE International Symposium on Hardware-Oriented Security and Trust, May 2014, Washington, United States. pp.25 - 31, ⟨10.1109/HST.2014.6855563⟩

Communication dans un congrès hal-01110463v1

Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology

Shivam Bhasin , Jean-Luc Danger , Tarik Graba , Yves Mathieu

ES4CPS, Mar 2014, Dresden, Germany. ⟨10.1145/2559627.2559628⟩

Communication dans un congrès hal-02412041v1

Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security

Emna Amouri , Shivam Bhasin , Yves Mathieu , Tarik Graba , Jean-Luc Danger et al.

FPL 2014 - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. pp.1--4, ⟨10.1109/FPL.2014.6927422⟩

Communication dans un congrès hal-01372613v1

Evaluation of delay PUFs on CMOS 65nm technology: ASIC vs FPGA

Zouha Cherif , Jean-Luc Danger , Florent Lozac'H , Yves Mathieu , Lilian Bossuet

International Workshop on Hardware and Architectural Support for Security and Privacy, HASP 2013, Jun 2013, Tel-Aviv, Israel. pp.Article n° 4

Communication dans un congrès hal-00859079v1

Design Methodology of an ASIC TRNG based on an open-loop delay chain

Molka Ben Romdhane , Jean-Luc Danger , Tarik Graba , Yves Mathieu

NEWCAS, Jun 2013, Paris, France. ⟨10.1109/NEWCAS.2013.6573654⟩

Communication dans un congrès hal-02411986v1

A Dual Threshold Voltage Technique for Glitch Minimization

Mariem Slimani , Philippe Matherat , Yves Mathieu

19th IEEE International Conference on Electronics, Circuits and Systems, Dec 2012, Séville, Spain. pp.444-447, ⟨10.1109/ICECS.2012.6463554⟩

Communication dans un congrès hal-01166345v1

Calibrating a predictive cache emulator for SoC design

Stéphane Mancini , Lionel Pierrefeu , Zahir Larabi , Yves Mathieu

NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Jun 2010, Anaheim, Californie, United States. pp.273-280, ⟨10.1109/AHS.2010.5546246⟩

Communication dans un congrès hal-02278686v1

Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints.

Laurent Sauvage , Sylvain Guilley , Jean-Luc Danger , Yves Mathieu , Maxime Nassar

Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09., Apr 2009, NICE, France. pp.640-645

Communication dans un congrès hal-00325417v3

Efficient data access management for FPGA-Based image processing SoCs

Zahir Larabi , Yves Mathieu , Stéphane Mancini

RSP 2009 - 20th IEEE/IFIP International Symposium on Rapid System Prototyping, Jun 2009, Paris, France. pp.159-165

Communication dans un congrès hal-00368532v2

Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow

Shivam Bhasin , Jean-Luc Danger , Florent Flament , Tarik Graba , Sylvain Guilley et al.

ReConFig, Dec 2009, Cancún, Mexico. pp.213 - 218, ⟨10.1109/ReConFig.2009.50⟩

Communication dans un congrès hal-00411843v3

High Efﬁciency Reconﬁgurable Cache for Image Processing

Zahir Larabi , Yves Mathieu , Stéphane Mancini

ERSA 2009 - 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, Jul 2009, Las Vegas USA, United States. pp.226-232

Communication dans un congrès hal-00384989v1

Security Evaluation of a Balanced Quasi-Delay Insensitive Library (SecLib)

Sylvain Guilley , Florent Flament , Yves Mathieu , Renaud Pacalet

Conference on Design of Circuits and Integrated Systems, Nov 2008, Grenoble, France. 6 p., ISBN: 978-2-84813-124-5

Communication dans un congrès hal-00283405v5

Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs

Sylvain Guilley , Laurent Sauvage , Jean-Luc Danger , Tarik Graba , Yves Mathieu

Secure System Integration and Reliability Improvement, Jul 2008, Yokohama, Japan. pp.16-23, ⟨10.1109/SSIRI.2008.31⟩

Communication dans un congrès hal-00259153v5

The “Backend Duplication” Method

Sylvain Guilley , Philippe Hoogvorst , Yves Mathieu , Renaud Pacalet

Workshop on Cryptographic Hardware and Embedded Systems (CHES), Aug 2005, Edinburgh, United Kingdom. pp.383-397, ⟨10.1007/11545262_28⟩

Communication dans un congrès hal-02893271v1

Post-layout Security Evaluation Methodology Against Probing Attacks

Sofiane Takarabt , Sylvain Guilley , Youssef Souissi , Laurent Sauvage , Yves Mathieu

Nguyen-Son Vo; Van-Phuc Hoang; Quoc-Tuan Vien. Industrial Networks and Intelligent Systems. 7th EAI International Conference, INISCOM 2021, Hanoi, Vietnam, April 22-23, 2021, Proceedings, 379, Springer International Publishing, pp.465-482, 2021, Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, 978-3-030-77423-3. ⟨10.1007/978-3-030-77424-0_37⟩

Chapitre d'ouvrage hal-03365004v1

Fault Analysis Assisted by Simulation

Kais Chibani , Adrien Facon , Sylvain Guilley , Damien Marion , Yves Mathieu et al.

Jakub Breier; Xiaolu Hou; Shivam Bhasin. Automated Methods in Cryptographic Fault Analysis, Springer International Publishing, pp.263-277, 2019, 978-3-030-11332-2. ⟨10.1007/978-3-030-11333-9_12⟩

Chapitre d'ouvrage hal-02915671v1