Cyrille LE ROYER
- Département Composants Silicium (DCOS)
Domaines de recherche
Compétences
Publications
Publications
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GaN and wide-bandgap semiconductor devices for power electronics applicationsAPWS 2024 - The 11th Asia-Pacific Workshop on Widegap Semiconductors, Oct 2024, Busan, South Korea |
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Temperature dependence of 1200V-10A SiC power diodes: impact of design and substrate on electrical performanceICSCRM 2024 - the International Conference on Silicon Carbide and Related Materials, Sep 2024, Raleigh, United States. pp.581-583, ⟨10.4028/b-f6NMEP⟩ |
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New insights using avalanche mode for pn-wafer evaluation of SiC diodes technology and design ruggednessISPSD 2024 - 36th International Symposium on Power Semiconductor Devices and ICs, Jun 2024, Brême, Germany. pp.176-179, ⟨10.1109/ISPSD59661.2024.10579466⟩ |
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DLTS Investigation of Implantation-induced Defects in 4H-SiC Power DiodesWOCSDICE-EXMATEC 2024, K. Zekentes and E. Iliopoulos, FORTH, Greece, May 2024, Heraklion, Greece |
Deep Insights into Recessed Gate MOS-HEMT Technology for Power Applications2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Mar 2023, Seoul, South Korea. ⟨10.1109/EDTM55494.2023.10102971⟩ |
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Recent Achievements in Recessed Gate MOS-channel HEMT TechnologyWOCSDICE - EXMATEC, May 2023, Palerme, Italy |
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Impact of gate morphology on electrical performances of recessed GaN-on Si MOS channel-HEMT for different channel orientationsISPSD 2023 - International Symposium on Power Semiconductor Devices and ICs, May 2023, Hong-Kong, Hong Kong SAR China. pp.382-385, ⟨10.1109/ISPSD57135.2023.10147642⟩ |
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Recent advances in GaN power devices development at CEA-LETIGaN MARATHON, Jun 2022, Venise, Italy |
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Gallium nitride power devices for power conversion applicationsENGE 2022 - The 7th International Conference on Electronic Materials and Nanotechnology for Green Environment, Nov 2022, Jeju, South Korea |
Y-unction based methodology for accurate statistical extraction of HEMT device parameters for GaN technologyEUROSOI-ULIS 2020 - Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, Sep 2020, Caen, France. pp.1-4, ⟨10.1109/EUROSOI-ULIS49407.2020.9365637⟩ |
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Innovative tunnel FET architectures2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Mar 2018, Granada, Spain. pp.25-28, ⟨10.1109/ULIS.2018.8354725⟩ |
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Z2-FET memory for low power applicationsSemiconductor Memories Workshop, 2017 ESSDERC, Sep 2017, Leuven, Belgium |
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Low-Power Z2-FET Capacitorless 1T-DRAM2017 IEEE International Memory Workshop (IMW), May 2017, Monterey, United States. pp.103-106, ⟨10.1109/IMW.2017.7939093⟩ |
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New features in planar SiGe channel tunnel FETs performance and operation2015 Silicon Nanoelectronics Workshop (SNW), Jun 2015, Kyoto, Japan. pp.91-92 |
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A lesson from archeology: The buried gates2015 Advanced Research Workshop Future Trends in Microelectronics: Journey into the Unknown, Jun 2015, Mallorca, Spain |
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First demonstration of ultrathin body c-SiGe channel FDSOI pMOSFETs combined with SiGe(:B) RSD: Drastic improvement of electrostatics (Vth,p tuning, DIBL) and transport (μ0, Isat) properties down to 23nm gate length2011 IEEE International Electron Devices Meeting (IEDM), Dec 2011, Washington, United States. pp.16.5.1-16.5.4, ⟨10.1109/IEDM.2011.6131567⟩ |
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A new memory concept: the Nano-Multiple-Tunnel-Junction memory with embedded Si nano-crystalsSilicon Nanoelectronics Workshop, 2002, Honolulu, United States. pp.Volume 72, Issues 1-4, Pages 399-404 |
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Coulomb Blockade in Thin SOI Nanodevices32nd European Solid-State Device Research Conference, Sep 2002, Firenze, France. pp.395-398, ⟨10.1109/ESSDERC.2002.194951⟩ |
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Normally-OFF 650V GaN-on-Si MOSc-HEMT Transistor: Benefits of the fully recessed gate architectureISPSD 2022 - IEEE 34th International Symposium on Power Semiconductor Devices and ICs, May 2022, Vancouver, Canada. 2022, ⟨10.1109/ISPSD49238.2022.9813672⟩ |
PROCEDE DE REALISATION D’UN DISPOSITIF ELECTRONIQUE A QUBIT(S) SUPRACONDUCTEUR(S) INCLUANT AU MOINS UN JOFETFrance, N° de brevet: FR3134910. 2022 |
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PROCÉDÉ DE RÉALISATION D'UN DISPOSITIF QUANTIQUEFrance, N° de brevet: FR3129564. 2021 |
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Transistor MOS à espaceurs d'airFrance, N° de brevet: FR3001831 (A1) 2014-08-08. N° de priorité : FR20130050941 20130204. 2014, pp.Numéro de demande: FR20130050941 20130204 |
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Procédé de formation de contacts de grille, de source et de drain sur un transistor MOSN° de brevet: FR2990295 (A1). 2013 |