Jean-Michel Gorius
Ingénieur de recherche
10
Documents
Affiliation actuelle
- Architectures matérielles spécialisées pour l’ère post loi-de-Moore (TARAN)
Identifiants chercheurs
Site web
Publications
9
9
6
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1
Publications
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Optimizing Recovery Logic in Speculative High-Level SynthesisDAC 2025 - 62nd Design Automation Conference, Jun 2025, San Fransisco, United States. pp.1-7, ⟨10.1109/dac63849.2025.11133015⟩
Communication dans un congrès
hal-05140504
v1
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A Unified Memory Dependency Framework for Speculative High-Level SynthesisCC 2024 - ACM SIGPLAN International Conference on Compiler Construction, Mar 2024, Edinburgh (Ecosse), United Kingdom. pp.1-13, ⟨10.1145/3640537.3641581⟩
Communication dans un congrès
hal-04394762
v2
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Exploration efficace d'espace de conception pour la synthèse de haut niveau dynamique et spéculativeCOMPAS 2024 - Conférence francophone d'informatique en Parallélisme, Architecture et Système, Jul 2024, Nantes, France. pp.1-8
Communication dans un congrès
hal-04615776
v1
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Efficient Design Space Exploration for Dynamic & Speculative High-Level SynthesisFPL 2024 - 34th International Conference on Field-Programmable Logic and Applications, Sep 2024, Turin, Italy. pp.1-9, ⟨10.1109/FPL64840.2024.00024⟩
Communication dans un congrès
hal-04615767
v2
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Design Exploration of RISC-V Soft-Cores through Speculative High-Level SynthesisFPT 2022 - International Conference on Field Programmable Technology, Dec 2022, Honk Kong / Hybrid, Hong Kong SAR China. pp.1-6, ⟨10.1109/ICFPT56656.2022.9974478⟩
Communication dans un congrès
hal-03828841
v1
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Speculative High-Level Synthesis of RISC-V ProcessorsRISC-V summit Europe 2025, May 2025, Paris, France. pp.1-1, 2025
Poster de conférence
hal-05140615
v1
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Optimizing Recovery Logic in Speculative High-Level SynthesisDAC 2025 - Design Automation Conference, Jun 2025, San francisco, United States
Poster de conférence
hal-05140532
v1
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Speculative High-Level Synthesis of RISC-V ProcessorsRISC-V Summit Europe 2024, Jun 2024, Munich, Germany. , 2024
Poster de conférence
hal-04615846
v1
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High-level synthesis of instruction set processorsHardware Architecture [cs.AR]. Université de Rennes, 2024. English. ⟨NNT : 2024URENS068⟩
Thèse
tel-04884873
v2
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SpecHLS: Speculative Accelerator Design using High-Level SynthesisIEEE Micro, In press, pp.1-10. ⟨10.1109/mm.2022.3188136⟩
Article dans une revue
hal-03714101
v1
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