Kevin Martin
Maître de conférences - Université de Bretagne Sud
62
Documents
Identifiants chercheurs
- kevin-martin
- 0000-0002-8122-1192
- IdRef : 147602300
Présentation
**Maitre de conférences - Associate Professor**
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### **Université de Bretagne-Sud**
Kevin Martin is an associate professor at the Université de Bretagne-Sud, France, in the ARCAD team of the Lab-STICC.
He has received a M.S. in electrical and computer engineering in 2004 and a PhD in computer science in 2010 from the Université de Rennes, France.
His research interests include system-level design and methodologies, CGRAs, memories, custom processors, embedded multi-processor platforms, high-level synthesis, computer-aided design for SoCs and embedded systems.
**Maitre de conférences - Associate Professor**
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### **Université de Bretagne-Sud**
Kevin Martin is an associate professor at the Université de Bretagne-Sud, France, in the team MOCS of the Lab-STICC.
He has received a M.S. in electrical and computer engineering in 2004 and a PhD in computer science in 2010 from the Université de Rennes, France.
His research interests include system-level design and methodologies, custom processors, embedded multi-processor platforms, high-level synthesis, computer-aided design for SoCs and embedded systems.
Publications
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Standalone Nested Loop Acceleration on CGRAs for Signal Processing ApplicationsDASIP 2024: Workshop on Design and Architectures for Signal and Image Processing, Jan 2024, Munich, Germany
Communication dans un congrès
hal-04505187v1
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Scratchy : A Class of Adaptable Architectures with Software-Managed Communication for Edge Streaming ApplicationsDASIP 2024: Workshop on Design and Architectures for Signal and Image Processing, Jan 2024, Munich (Allemagne), Germany
Communication dans un congrès
hal-04509310v1
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Ultra-low Power Computing with CGRAs an architecture, compilation, and application triptychWorkshop on Reconfigurable Computing (WRC), Jun 2022, Budapest, France
Communication dans un congrès
hal-03704282v1
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ManyGUI: A Graphical Tool to Accelerate Many-core Debugging Through Communication, Memory, and Energy ProfilingDroneSE and RAPIDO '22: System Engineering for constrained embedded systems, Jun 2022, Budapest, Hungary. pp.39-46, ⟨10.1145/3522784.3522791⟩
Communication dans un congrès
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Mitigating Transceiver and Token Controller Permanent Faults in Wireless Network-on-ChipEuromicro International Conference on Parallel, Distributed and Network-based Processing, Mar 2022, Valladolid, Spain
Communication dans un congrès
hal-03609150v1
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Twenty Years of Automated Methods for Mapping Applications on CGRA2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), May 2022, Lyon, France. ⟨10.1109/IPDPSW55747.2022.00118⟩
Communication dans un congrès
hal-03704256v1
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On Cache Limits for Dataflow Applications and Related Efficient Memory Management StrategiesDASIP 2021: Workshop on Design and Architectures for Signal and Image Processing, Jan 2021, Budapest -Online, Hungary. ⟨10.1145/3441110.3441573⟩
Communication dans un congrès
hal-03125551v1
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Hardware Based Loop Optimization for CGRA ArchitecturesApplied Reconfigurable Computing. Architectures, Tools, and Applications, Jun 2021, Rennes, France. pp.65-80, ⟨10.1007/978-3-030-79025-7_5⟩
Communication dans un congrès
hal-03345346v1
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TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuREDesign, Automation and Test in Europe Conference (DATE), Mar 2020, Grenoble, France
Communication dans un congrès
hal-02510931v1
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Energy Efficient Acceleration of Floating Point Applications onto CGRAICASSP, May 2020, Barcelona, Spain
Communication dans un congrès
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Context-memory Aware Mapping for Energy Efficient Acceleration with CGRAsDesign, Automation and Test in Europe Conference (DATE), Mar 2019, Florence, Italy
Communication dans un congrès
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Subutai: Distributed Synchronization Primitives in NoC Interfaces for Legacy Parallel-Applicationsthe 55th Annual Design Automation Conference, Jun 2018, San Francisco, United States. pp.83:1--83:6, ⟨10.1145/3195970.3196124⟩
Communication dans un congrès
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Broadcast- and Power-Aware Wireless NoC for Barrier Synchronization in Parallel Computing2018 31st IEEE International System-on-Chip Conference (SOCC), Sep 2018, Arlington, United States. pp.1-6
Communication dans un congrès
hal-02005970v1
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Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore ArchitecturesPARMA-DITAM, Jan 2018, Manchester, United Kingdom. ⟨10.1145/3183767.3183780⟩
Communication dans un congrès
hal-01704702v1
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Une approche basée sur la programmation par contraintes pour résoudre le problème d'affectation de binômesROADEF, Feb 2018, Lorient, France
Communication dans un congrès
hal-01724696v1
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A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data AnalyticsInternational Symposium on Circuits and Systems (ISCAS), May 2018, Florence, Italy
Communication dans un congrès
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Efficient Mapping of CDFG onto Coarse-Grained Reconfigurable Array ArchitecturesASP-DAC, Jan 2017, Tokyo, Japan
Communication dans un congrès
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A 142MOPS/mW Integrated Programmable Array accelerator for Smart Visual ProcessingIEEE International Symposium on Circuits & Systems, May 2017, Baltimore, United States
Communication dans un congrès
hal-01534574v1
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Notifying Memories: a case-study on Data-Flow Applications with NoC Interfaces ImplementationDesign Automation Conference, Jun 2016, Austin, United States. ⟨10.1145/2897937.2898051⟩
Communication dans un congrès
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Introduction d'aléas dans le processus de projection d'applications sur CGRAConférence d’informatique en Parallélisme, Architecture et Système (COMPAS 2016), Lab-STICC (UMR 6285), Jul 2016, Lorient, France
Communication dans un congrès
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A Scalable Design Approach to Efficiently Map Applications on CGRAsIEEE Computer Society Annual Symposium on VLSI, Jul 2016, Pittsburgh, United States. pp.7560275, ⟨10.1109/ISVLSI.2016.54⟩
Communication dans un congrès
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Improving Reuse by means of Asymmetrical Model Migrations: An Application to the Orcc Case Study2015 ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MODELS), Sep 2015, Ottawa, Canada
Communication dans un congrès
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COMPA backend : Runtime dynamique pour l’exécution de programmes flot de données sur plates-formes multiprocesseursCOMPAS 2015 : - Conférence d’informatique en Parallélisme, Architecture et Système, Jun 2015, Lille, France. pp.1-9
Communication dans un congrès
hal-01167037v1
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Communication-model based Embedded Mapping of Dataflow Actors on Heterogeneous MPSoCConference on Design and Architectures for Signal and Image Processing (DASIP), Oct 2014, Madrid, France
Communication dans un congrès
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Virtual Devices for Hot-Pluggable Processors17th Euromicro Conference on Digital System Design (DSD), Aug 2014, Verona, Italy
Communication dans un congrès
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Dataflow program implementation onto a heterogeneous multiprocessor platformMETODO, Oct 2014, Madrid, France
Communication dans un congrès
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Ordonnancement, assignation et transformations dynamiques de graphe simultanés pour projeter efficacement des applications sur CGRAsComPAS 2014 : conférence en parallélisme, architecture et systèmes, Apr 2014, Neuchatel, Suisse
Communication dans un congrès
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An automated design approach to map applications on CGRAsGLSVLSI Great Lakes Symposium on VLSI, May 2014, Houston, Texas, United States. pp.229-230, ⟨10.1145/2591513.2591552⟩
Communication dans un congrès
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Efficient Application Mapping on CGRAs based on Backward Simultaneous Scheduling/Binding and Dynamic Graph TransformationsIEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Jun 2014, Zurich, Switzerland. pp.6868652, ⟨10.1109/ASAP.2014.6868652⟩
Communication dans un congrès
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Virtual UARTs for Reconfigurable Multi-processor ArchitecturesIEEE 27th International Symposium on Parallel and Distributed Processing, May 2013, United States. pp.Pages 252-259
Communication dans un congrès
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GeCoS: A framework for prototyping custom hardware design flows13th IEEE International Working Conference on Source Code Analysis and Manipulation (SCAM), Sep 2013, Eindhoven, Netherlands. pp.100-105, ⟨10.1109/SCAM.2013.6648190⟩
Communication dans un congrès
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Sélection d'instructions et ordonnancement parallèle simultanés pour la conception de processeurs spécialisésSymposium en Architecture de Machines (Sympa'14), May 2011, St Malo, France
Communication dans un congrès
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Graph Constraints in Embedded System DesignWorshop on Combinatorial Optimization for Embedded System Design (COESD 2010), Jun 2010, Bologne, Italy
Communication dans un congrès
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Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system20th IEEE International Conference on Application-specific Systems, Architectures and Processors, (ASAP 2009), Jul 2009, Boston, United States. pp.145-152, ⟨10.1109/ASAP.2009.19⟩
Communication dans un congrès
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Sélection automatique d'instructions et ordonnancement d'applications basés sur la programmation par contraintes13ème Symposium en Architecture de machines (SympA'13), Sep 2009, Toulouse, France
Communication dans un congrès
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Design of Processor Accelerators with Constraints8th workshop of the Network for Sweden-based researchers and practitioners of Constraint programming, May 2009, Linköping, Sweden
Communication dans un congrès
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Constraint-Driven Identification of Application Specific Instructions in the DURASE System9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2009), Jul 2009, Samos, Greece. pp.194-203, ⟨10.1007/978-3-642-03138-0_21⟩
Communication dans un congrès
inria-00449798v1
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How Constraints Programming Can Help You in the Generation of Optimized Application Specific Reconfigurable Processor ExtensionsInternational Conference on Engineering of Reconfigurable Systems & Algorithms (ERSA 2009), Jul 2009, Las Vegas, United States
Communication dans un congrès
inria-00449775v1
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Procédé et dispositif de tolérance aux fautes sur des composants électroniquesFrance, N° de brevet: FR1460633. 2015
Brevet
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Procédé et dispositif d'architecture configurable à gros grains pour exécuter l'intégralité d'un codeFrance, N° de brevet: FR1460631. 2015
Brevet
hal-01166875v1
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Prise en compte de la contrainte de mémoire de programme dans un flot de compilation pour CGRA2019
Autre publication scientifique
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Compiling for notifying memories: issues and challenges2019
Autre publication scientifique
hal-02494373v1
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Move Based Algorithm for Runtime Mapping of Dataflow Actors on Heterogeneous MPSoCs2017
Autre publication scientifique
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Génération automatique d'extensions de jeux d'instructions de processeursGénie logiciel [cs.SE]. Université Rennes 1, 2010. Français. ⟨NNT : ⟩
Thèse
tel-00526133v1
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Mapping parallel applications on parallel architecturesHardware Architecture [cs.AR]. Université Bretagne Sud, 2023
HDR
tel-04054474v2
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On-chip memories at the edgeDoctoral. France. 2022
Cours
hal-03710634v1
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Mémoires sur puce : architecture et organisationDoctorat. France. 2019
Cours
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