Nadine Azemard
Présentation
Publications
Publications
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Iterative Method for Performance Prediction Improvement of Integrated CircuitsDCIS 2021 - 36th Conference on Design of Circuits and Integrated Systems, Nov 2021, Vila do Conde, Portugal. pp.1-5, ⟨10.1109/DCIS53048.2021.9666182⟩ |
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Oscillatory Neural Networks for Edge AI ComputingISVLSI 2021 - IEEE Computer Society Annual Symposium on VLSI, Jul 2021, Tampa, United States. pp.326-331, ⟨10.1109/ISVLSI51109.2021.00066⟩ |
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NeurONN: Neuromorphic Computing for Artificial Intelligence at the Edge3rd AI Compute Symposium (IBM IEEE CAS/EDS), Oct 2020, Zurich (virtual), Switzerland |
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EU H2020 NEURONN: Two-Dimensional Oscillatory Neural Networks for Energy Efficient Neuromorphic ComputingEFECS 2020 - European Forum for Electronic Components and Systems, Nov 2020, Brussels, Belgium |
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Stretchable Strain Sensors for Human Movement MonitoringDTIP 2020 - 22nd Symposium on Design, Test, Integration & Packaging of MEMS and MOEMS, Jun 2020, (Virtual ), France. ⟨10.1109/DTIP51112.2020.9139154⟩ |
Combined analysis of supply voltage and body-bias voltage for energy managementPATMOS: Power And Timing Modeling, Optimization and Simulation, Jul 2018, Platja d’Aro, Spain. pp.88-91, ⟨10.1109/PATMOS.2018.8464159⟩ |
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Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic LogicICRC: International Conference on Rebooting Computing, Nov 2017, Washington, DC, United States. ⟨10.1109/ICRC.2017.8123661⟩ |
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Atomistic to circuit level modeling of defective doped SWCNTs with contacts for on-chip interconnect applicationNMDC: Nanotechnology Materials and Devices Conference, Oct 2017, Singapore, Singapore. pp.66-67, ⟨10.1109/NMDC.2017.8350506⟩ |
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Physical description and analysis of doped carbon nanotube interconnectsPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2016, Brême, Germany. pp.250-255, ⟨10.1109/PATMOS.2016.7833695⟩ |
Statistical Energy Study for 28nm FDSOI TechnologyVARI: Workshop on CMOS Variability, Sep 2015, Salvador, Bahia, Brazil |
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Statistical Energy Study for 28nm FDSOI DevicesEuroSimE: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, Apr 2015, Budapest, Hungary. ⟨10.1109/EuroSimE.2015.7103149⟩ |
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VARI Worshop OverviewDCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.159-161 |
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Statistical Cells Timing Metrics CharacterizationFTFC: Faible Tension - Faible Consommation, Jun 2012, Paris, France |
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Characterizing Statistical Cells Timing Metrics with Semi-Monte-Carlo MethodVLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2011, Hong-Kong, China |
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Statistical Timing Characterization of Standard Cells with Semi-Monte-Carlo MethodVARI: Workshop on CMOS Variaility, May 2011, Grenoble, France |
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On-Chip Process Variability MonitoringVARI: Workshop on CMOS Variability, May 2010, Montpellier, France |
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Voltage Scaling and Body Biasing Methodology for High Performance Hardwired LDPCICICDT: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.82-85, ⟨10.1109/ICICDT.2010.5510289⟩ |
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Computing Delay Correlations in SSTAICICDT: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.130-133, ⟨10.1109/ICICDT.2010.5510277⟩ |
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SSTA with Delay CorrelationsNEWCAS: New Circuits and Systems, Jun 2010, Montreal, QC, Canada. pp.261-266, ⟨10.1109/NEWCAS.2010.5603930⟩ |
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SSTA with Cell-to-Cell Delay CorrelationsVARI: Workshop on CMOS Variability, May 2010, Montpellier, France |
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Interpretation of SSTA ResultsFTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Switzerland |
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Product On-Chip Process Compensation for Low Power and Yield EnhancementPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.247-255, ⟨10.1007/978-3-642-11802-9_29⟩ |
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Digital Timing Slack Monitors and their Specific Insertion Flow for Adaptive Compensation of VariabilitiesPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.266-275, ⟨10.1007/978-3-642-11802-9_31⟩ |
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Un nouveau système d'instrumentation en ligne pour la caractérisation et l'adaptation dynamique aux variationsFTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Suisse |
An Innovative Timing Slack Monitor for Variation Tolerant CircuitsICICDT 2009 - IEEE International Conference on IC Design and Technology, May 2009, Austin, TX, United States. pp.215-218, ⟨10.1109/ICICDT.2009.5166299⟩ |
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On-Chip Process Variability MonitoringDATE: Design, Automation and Test in Europe, Apr 2009, Nice, France |
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Interpreting SSTA Results with CorrelationPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.16-25, ⟨10.1007/978-3-642-11802-9_6⟩ |
On-Chip Timing Slack MonitoringVLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2009, Florianopolis, Brazil. pp.89-94, ⟨10.1109/VLSISOC.2009.6041336⟩ |
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SSTA with Correlations Considering input Slope and Output Load VariationsVLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2008, Rhodes Island, Greece. pp.164-167 |
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Étude des violations de temps d'établissement et de maintien dues aux variations du processus de fabrication dans un opérateur arithmétiqueJNRDM 2008 - 11e Journées Nationales du Réseau Doctoral de Microélectronique, May 2008, Bordeaux, France |
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A Comparative Study of Variability Impact on Static Flip-Flop Timing CharacteristicsICICDT 2008 - IEEE International Conference on IC Design and Technology, Jun 2008, Grenoble, France. pp.167-170, ⟨10.1109/ICICDT.2008.4567271⟩ |
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Impact de la variabilité des caractéristiques temporelles des cellules combinatoires et séquentielles sur un opérateur numériqueFTFC: Faible Tension - Faible Consommation, May 2008, Louvain-La-Neuve, Belgique |
SSTA Considering Effects of Structure Correlations, Input Slope and Output Load VariationsFTFC: Faible Tension - Faible Consommation, May 2008, Louvain-la-Neuve, Belgium. pp.39-43 |
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Conditional Moments based SSTA Considering Switching Process Induced CorrelationsDCIS: Design of Circuits and Integrated Systems, Nov 2008, Grenoble, France. pp.70-77 |
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SSTA with Structure Correlations Considering input Slope and Output Load VariationsGDR SOC-SIP, Jun 2008, Paris, France. pp.3 |
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SSTA Considering Switching Process Induced CorrelationsAPCCAS: Asia Pacific Conference on Circuits and System, Nov 2008, Macao, China. pp.562-565, ⟨10.1109/APCCAS.2008.4746085⟩ |
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Setup and Hold Timing Violations Induced by Process Variations, in a Digital MultiplierISVLSI: International Symposium on Very Large Scale Integration, Apr 2008, Montpellier, France. pp.316-321, ⟨10.1109/ISVLSI.2008.70⟩ |
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A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin EvaluationFTFC: Faible Tension - Faible Consommation, May 2007, Paris, France. pp.19-25 |
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Une Famille d'Additionneurs Asynchrones CMOS Bundled Data à Temps de Calcul Dépendant aux DonnéesFTFC: Faible Tension - Faible Consommation, May 2007, Paris, France. pp.75-80 |
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Temperature and Voltage Aware Timing Analysis: Application to Voltage DropsDATE: Design, Automation and Test in Europe, Mar 2007, Nice, France. ⟨10.1109/DATE.2007.364426⟩ |
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A Simple Statistical Timing Analysis Flow and its Application to Timing Margin EvaluationPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden. pp.138-147, ⟨10.1007/978-3-540-74442-9_14⟩ |
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Une Famille d'Additionneur Asynchrones CMOS à Temps de Calcul Dépendant de DonnéesJNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France. pp.469-472 |
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Statistical Characterization of Library Timing PerformancePATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2006, Montpellier, France. pp.468-476, ⟨10.1007/11847083_45⟩ |
Request-Skip Adders: CMOS Standard Cell Data Dependent AddersICECS: International Conference on Electronics, Circuits and Systems, Dec 2006, Nice, France. pp.510-513, ⟨10.1109/ICECS.2006.379837⟩ |
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Circuit Performance Optimization under Delay ConstraintsDCIS: Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain |
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Timing Analysis in Presence of Supply Voltage and Temperature VariationsISPD: International Symposium on Physical Design, Apr 2006, San Jose, CA, United States. pp.10-16, ⟨10.1145/1123008.1123012⟩ |
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Exploration of the Area-Latency Tradeoff of Asynchronous CMOS data Dependent AddersDCIS: Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain |
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Timing Analysis in Presence of Voltage Drops and Temperature GradientsTAU: Timing Issues in the Specification and Synthesis of Digital Systems, Feb 2006, San Jose, CA, United States. pp.28-34 |
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Circuit Sizing Method under Delay ConstraintISCAS: International Symposium on Circuits and Systems, May 2006, Island of Kos, Greece. pp.5123-5126, ⟨10.1109/ISCAS.2006.1693785⟩ |
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Optimization Protocol Based on Low Power MetricsIWLS: International Workshop on Logic Synthesis, Jun 2005, Lake Arrowhead Resort, CA, United States. pp.288-293 |
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Path Optimization Protocol Based on Speed Low Power MetricsEUROCON: International Conference on "Computer as a Tool", Nov 2005, Belgrade, Serbia. pp.523-526, ⟨10.1109/EURCON.2005.1629980⟩ |
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Temperature Dependency in UDSM ProcessPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.693-703, ⟨10.1007/11556930_71⟩ |
Circuit Optimization Based on Speed IndicatorsICECS: International Conference on Electronics, Circuits and Systems, Dec 2005, Gammarth, Tunisia. pp.167-170, ⟨10.1109/icecs.2005.4633585⟩ |
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Low Power Oriented CMOS Circuit Optimization ProtocolDATE 2005 - 8th Design, Automation and Test in Europe Conference and Exhibition, Mar 2005, Munich, Germany. pp.640-645, ⟨10.1109/DATE.2005.202⟩ |
Additionneurs RCA Data Dependent MicropipelinesFTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.183-188 |
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Protocole d'Optimisation de Circuit CMOS Orienté Basse PuissanceFTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.17-22 |
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Speed Indicators for Circuit OptimizationPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.618-628, ⟨10.1007/11556930_63⟩ |
Ripple Carry Adder for Micropipeline CircuitsDCIS 2005 - 20th Conference on Design of Circuits and Integrated Systems, Nov 2005, Lisbonne, Portugal |
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Synthèse Physique et Optimisation des Performances au Niveau TransistorFTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.91-95 |
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Design Optimization with Automated Cell GenerationPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.722-731, ⟨10.1007/978-3-540-30205-6_74⟩ |
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Physical Extension of the Logical Effort ModelPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.838-848, ⟨10.1007/978-3-540-30205-6_86⟩ |
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RC on-chip interconnect Performance revisitedDCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.809-814 |
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Definition of P/N Width Ratio for CMOS Standard Cell LibraryDCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.769-773 |
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Temperature Dependence in Low Power CMOS UDSM ProcessPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.111-118, ⟨10.1007/978-3-540-30205-6_13⟩ |
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Performance Metric Based Optimization ProtocolPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.100-109, ⟨10.1007/978-3-540-30205-6_12⟩ |
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Delay Bound Based CMOS Gate Sizing TechniqueISCAS: International Symposium on Circuits and Systems, May 2004, Vancouver, BC, Canada. pp.189-192, ⟨10.1109/ISCAS.2004.1329494⟩ |
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Optimization Protocol Based on Performance MetricDCIS 2004 - 19th International Conference on Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.964-968 |
Automatic Layout Synthesis Based Performance OptimizationIWLS: International Workshop on Logic Synthesis, Jun 2004, Temecula, CA, United States. pp.80-85 |
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Représentation Unifiée des Performances Temporelles d'une Bibliothèque de Cellules StandardsFTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.119-124 |
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Dimensionnement de Portes CMOS Sous Contrainte de DélaiFTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.111-117 |
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CMOS Gate Sizing under Delay ConstraintPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2003, Torino, Italy. pp.60-69, ⟨10.1007/978-3-540-39762-5_8⟩ |
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Continuous Representation of the Performance of a CMOS LibraryESSCIRC: European Solid-State Circuits Conference, Sep 2003, Estoril, Portugal. pp.595-598, ⟨10.1109/ESSCIRC.2003.1257205⟩ |
Timing Performance Representation of a CMOS Standard Cell LibraryDCIS: Design of Circuits and Integrated Systems, Nov 2003, Ciudad Real, Spain. pp.83-88 |
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Metric Definition for Circuit Speed OptimizationPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2003, Turin, Italy. pp.451-460 |
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Metric Definition for Circuit Speed OptimizationIWLS: International Workshop on Logic Synthesis, May 2003, Laguna Beach, CA, United States |
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Définition d'une Métrique d'Insertion de BuffersFTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.131-136 |
Gate Speed Improvement at Minimal Power DissipationAPPCAS: Asia-Pacific Conference on Circuits and Systems, Oct 2002, Denpasar, Bali, pp.278-282 |
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Metric Definition for Buffer InsertionDCIS: Design of Circuits and Integrated Systems, Nov 2002, Santander, Spain. pp.307-312 |
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Evaluation et Optimisation de Chemins CombinatoiresColloque du GDR CAO de Circuits et Systèmes Intégrés, May 2002, Paris, France. pp.173-176 |
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Structure Independent Representation of Output Transition Time for CMOS LibraryPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2002, Seville, Spain. pp.247-257, ⟨10.1007/3-540-45716-X_25⟩ |
Defining the Maximum Speed of CMOS Gate LibraryDCIS: Design of Circuits and Integrated Systems, Nov 2002, Santander, Spain. pp.81-86 |
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Deep Submicron Switching Current Modeling for CMOS Logic Output Transition Time DeterminationPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2001, Yverdon-Les-Bains, Switzerland. pp.5.3.1-5.3.10 |
Delay Bound Determination for Timing Closure on CMOS CircuitsIWLS: International Workshop on Logic and Synthesis, Jun 2001, Granlibakken Conference Center, United States. pp.96-100 |
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Full Analyttical Model for delay Performance Estimation in Submicron CMOSMIXDES: Mixed Design of Integrated Circuits and Systems, Jun 2001, Zakopane, Poland. pp.355-359 |
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Performance Indicators for Designing CMOS LogicICM: International Conference on Microelectronics, Oct 2001, Rabat, Morocco. pp.99-102, ⟨10.1109/ICM.2001.997497⟩ |
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Timing Closure Management based on Delay Bound DeterminationVLSI-SoC: Very Large Scale Integration - System-on-Chip, Dec 2001, Montpellier, France. pp.430-434 |
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Technological Assignment for a Minimal Power ConsumptionVLSI-SoC: Very Large Scale Integration - System-on-Chip, Dec 2001, Montpellier, France. pp.236-241 |
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Switching Current Modeling in CMOS Inverter for Speed and Power EstimationDCIS: Design of Circuits and Integrated Systems, Nov 2001, Porto, Portugal. pp.618-622 |
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Delay Bound Determination for Timing Closure SatisfactionISCAS: International Symposium on Circuits and Systems, May 2001, Sydney, NSW, Australia. pp.375-378, ⟨10.1109/ISCAS.2001.922063⟩ |
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A Physical Synthesis Design Flow based on Virtual ComponentsDCIS: Design of Circuits and Integrated Systems, Nov 2000, Montpellier, France. pp.740-745 |
POPS: A tool for Delay/Power Performance/OptimizationASIC-SoC: International ASIC/SOC Conference, Sep 2000, Arlington, VA, United States. pp.276-280, ⟨10.1109/ASIC.2000.880715⟩ |
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Upper and Lower bound Determination of delay on Critical PathDCIS: Design of Circuits and Integrated Systems, Nov 2000, Montpellier, France. pp.543-547 |
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Delay Bound Determination for Path Constraint SatisfactionISMA: International Symposium on Microelectronics and Assembly, Nov 2000, Singapour, China. pp.122-129, ⟨10.1117/12.405403⟩ |
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Delay-Power Performance AnalysisICECS: International Conference on Electronics, Circuits and Systems, Sep 1999, Pafos, Cyprus. pp.1543-1546, ⟨10.1109/ICECS.1999.814465⟩ |
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Local Gate Resizing for Critical Path OptimizationDCIS: Design of Circuits and Integrated Systems, Nov 1999, Palma de Majorque, Spain. pp.195-200 |
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Satisfaction of Delay/Power Constraints by Iterative Gate SizingPATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1999, Kos, Greece. pp.325-334 |
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Post Layout Management of Delay Power Constraints in Submicronic CMOS ImplementationIWLS: International Workshop on Logic Synthesis, Jun 1999, Lake Tahoe, CA, United States. pp.198-201 |
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A New Tool for Path Performance OptimizationInternational Workshop on IP Based Synthesis and System Design, Dec 1998, Grenoble, France. pp.175-179 |
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Long and Short Path Sizing for Delay-Power Performance ManagementIWLS: International Workshop on Logic Synthesis, Jun 1998, Lake Tahoe, CA, United States |
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Path Resizing Based on Incremental TechniqueISCAS: International Symposium on Circuits and Systems, May 1998, Monterey, CA, United States. pp.90-93, ⟨10.1109/ISCAS.1998.705219⟩ |
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Path Selection for Delay and Power Performance OptimizationSAME: Sophia Antipolis Forum on Microelectronics, Oct 1998, Sophia Antipolis, France. pp.48-53 |
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POPS: Performance Optimization by Path SelectionDCIS: Design of Circuits and Integrated Systems, Nov 1998, Madrid, Spain. pp.10-15 |
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POPS: A New Tool for Path EvaluationPATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1998, Lyngby, Denmark. pp.235-244 |
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Selective Gate Sizing for Delay/Power Performance ManagementIWLAS: International Workshop on Logic and Architecture Synthesis, Dec 1997, Grenoble, France |
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A Path Sensitization Approach for Performance OptimizationISIC: International Symposium on IC Technology, Systems and Applications, Sep 1997, Singapore, China. pp.94-97 |
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Performance Otimization by Path SelectionIWLS: International Workshop on Logic Synthesis, May 1997, Tahoe City, CA, United States. pp.152-155 |
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Path Sensitization for Performance OptimizationMIXDES: Mixed Design of Integrated Circuits and Systems, Jun 1997, Poznan, Poland. pp.195-200 |
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A Path Selection Algorithm for Performance OptimizationIWLAS: International Workshop on Logic and Architecture Synthesis, Dec 1996, Grenoble, France. pp.277-284 |
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Design and Selection of Buffers for Minimum Power-Delay ProductED&TC: European Design and Test Conference, Mar 1996, Paris, France. pp.224-228, ⟨10.1109/EDTC.1996.494153⟩ |
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Explicit Evaluation of Short Circuit Power Dissipation for CMOS Logic StructuresISLPD: International Symposium on Low Power Design, Apr 1995, Dana Point, CA, United States. pp.129-134, ⟨10.1145/224081.224104⟩ |
Design and Sizing of Tapered Buffers for Minimum Power-Delay ProductPATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1995, Oldenburg, Germany. pp.79-90 |
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Short-Circuit Power Dissipation calculation on CMOS Inverters using the Equivalent Short-Circuit Capacitance ConceptPATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1995, Oldenburg, Germany. pp.213-224 |
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Standard Cell Performance ModellingPATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1994, Barcelone, Spain. pp.158-167 |
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General Determination of Buffer Insertion LimitsIWoDA: International Workshop on Design Automation, Jun 1994, Moscou, Russia. pp.21-23 |
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A Real Characterization based Buffer Selection AlgorithmPATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1993, La Grande Motte, France |
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Tool Box for Performance Driven Macrocell layout SynthesisEurochip Workshop on VLSI Design Training, Sep 1993, Toledo, Spain. pp.56-61 |
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Evaluation of Speed up Strategy from Gate Performance ModellingIFIP Workshop on Logic and Architecture Synthesis, Dec 1993, Grenoble, France, pp.193-208 |
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Flexible Macrocell layout Generator4th ACM/SIGDA Physical Design Workshop, Layout Synthesis for the New Generation of VLSI ASIC Technologies, Apr 1993, UCLA Conference Center, CA, USA, pp.105-116 |
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P.SIZE: A Sizing aid for Optimized DesignsEURODAC 1992 - European Design Automation Conference, Sep 1992, Hamburg, Germany. pp.160-166, ⟨10.1109/EURDAC.1992.246248⟩ |
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Optimization Technique for Performance driven Cell GeneratorEuroASIC 1992 - European Conference on Application Specific Integrated Circuits, Jun 1992, Paris, France. pp.152-155, ⟨10.1109/EUASIC.1992.228032⟩ |
Application of Explicit Delay Time Modelling to CMOS Data Path Evaluation and Transistor SisingPATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 1992, Paris, France. pp.102-108 |
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An Accurate and Efficient Delay Time Modelling and its Application to CMOS Data Path Evaluation and Transistor SizingWorld Congress on Computation and Applied Mathematics, IMACS: International Association for Mathematics and Computers in Simulation, Jul 1991, Dublin, Ireland. pp.1661-1663 |
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Formal Sizing Rules of CMOS CircuitsEDAC 1991 - European Conference on Design Automation, Feb 1991, Amsterdam, Netherlands. pp.96-100, ⟨10.1109/EDAC.1991.206368⟩ |
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Evaluation of VLSI Layout Implementation for EfficiencyEURO-ASIC 1991 - European Conference on Design Automation with European Event in ASIC Design, May 1991, Paris, France. pp.362-365, ⟨10.1109/EUASIC.1991.212836⟩ |
CMOS Circuit Speed Optimization based on Closed form EquationInternational Students Microelectronic Conference, May 1990, Zagreb, Yugoslavia, pp.29-32 |
Digital Oscillatory Neural Networks for AI Edge Applications17e Colloque National du GDR SoC², Jun 2023, Lyon, France |
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Digital Oscillatory Neural Networks for AI Edge Applications16e Colloque National du GDR SoC², Jun 2022, Strasbourg, France. |
Mobile Robot Obstacle Avoidance with Oscillatory Neural Networks on FPGAIBM-IEEE AI Compute Symposium, Oct 2021, Virtual, France |
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Méthode Itérative pour l’Amélioration de la Prédiction des Performances des Circuits Intégrés15e Colloque National du GDR SoC², Jun 2021, Rennes, France |
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EU H2020 NeurONN: Two-Dimensional Oscillatory Neural Networks for Energy Efficient Neuromorphic ComputingEuroNanoForum 2021, May 2021, Braga, Portugal |
SmartVista: Smart Autonomous Multi Modal Sensors for Vital Signs MonitoringWorkshop on ‘Smart Bioelectronic and Wearable Systems’, Oct 2019, Brussels, Belgium. , 2019 |
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Piezoelectric Sensors Based on 1D/2D Materials for Smart Health Monitoring IoT13e Colloque National du GDR SoC², Jun 2019, Montpellier, France. , 2019 |
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Statistical Timing CharacterizationSoC: System on Chip, Oct 2012, Tampere, Finland. International Symposium on System on Chip, 2012, ⟨10.1109/ISSoC.2012.6376360⟩ |
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Towards Autonomous Scalable Integrated SystemsDesign Technology for Heterogeneous Embedded Systems, Springer, pp.63-89, 2012, 978-94-007-1124-2. ⟨10.1007/978-94-007-1125-9_4⟩ |
Modeling for Designing in Deep Sub-Micron TechnologiesPIGUET C. Low-Power Electronics Design, CPR Press, 2004, 0-8493-1941-2 |
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Gate Sizing for Low Power DesignSOC Design Methodologies, 90, Kluwer Academic Publishers, pp.301-312, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_26⟩ |
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Feasible delay Bound DefinitionSOC Design Methodologies, 90, Kluwer Academic Publishers, pp.325-335, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_40⟩ |
Path Selection Based on Incremental TechniqueMixed Design of Integrated Circuits and Systems, Kluwer Academic Publishers, pp.137-142, 1998 |
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Two-Dimensional Oscillatory Neural Networks for Energy Efficient Neuromorphic Computing2020 |
Contrat CEE MARLOW : Premier Rapport d'Avancement du Projet (PPR1)2003 |
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Contrat CEE MARLOW : Premier Rapport de Management du Projet (PMR1)2003 |
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A Central Market Place for Dissemination of Low Power Microelectronics Design Knowledge2003 |
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Library Free Integrated Circuits for Submicron Technologies[Research Report] Lirmm, University of Montpellier. 2002 |
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Library free integrated circuit design for submicron technologies2002 |
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Library Free Integrated Circuit Design for Submicron Technologies2000 |