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Nadine Azemard

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A mixed-signal oscillatory neural network for scalable analog computations in phase domain

Corentin Delacour , Stefania Carapezzi , Gabriele Boschetto , Madeleine Abernot , Thierry Gil
Neuromorphic Computing and Engineering, 2023, 3, pp.034004. ⟨10.1088/2634-4386/ace9f5⟩
Journal articles lirmm-04290523v1
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Oscillatory neural network learning for pattern recognition: an on-chip learning perspective and implementation

Madeleine Abernot , Nadine Azemard , Aida Todri-Sanial
Frontiers in Neuroscience, 2023, 17, pp.119679. ⟨10.3389/fnins.2023.1196796⟩
Journal articles hal-04129945v1
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Review—Energy Autonomous Wearable Sensors for Smart Healthcare: A Review

Abhishek Singh Dahiya , Jérôme Thireau , Jamila Boudaden , Swatchith Lal , Umair Gulzar
Journal of The Electrochemical Society, 2020, JES Focus Issue on Sensor Reviews, 167 (3), pp.037516. ⟨10.1149/2.0162003JES⟩
Journal articles lirmm-02387984v1
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1D Nanomaterial‐Based Highly Stretchable Strain Sensors for Human Movement Monitoring and Human–Robotic Interactive Systems

Abhishek Singh Dahiya , Thierry Gil , Jérôme Thireau , Nadine Azemard , Alain Lacampagne
Advanced Electronic Materials, 2020, 6 (10), pp.2000547. ⟨10.1002/aelm.202000547⟩
Journal articles lirmm-02932782v1

Energy Study for 28 nm Fully Depleted Silicon-On-Insulator Devices

Rida Kheirallah , Gilles R. Ducharme , Nadine Azemard
Journal of Low Power Electronics, 2016, 12 (1), pp.58-63. ⟨10.1166/jolpe.2016.1420⟩
Journal articles lirmm-01295833v1

Delay-correlation-aware SSTA based on conditional moments

Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme
Microelectronics Journal, 2012, 43 (4), pp.263-273. ⟨10.1016/j.mejo.2012.01.003⟩
Journal articles lirmm-00761821v1
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Timing Slack Monitoring under Process and Environmental Variations: Application to a DSP Performance Optimization

Philippe Maurine , Bettina Rebaud , Marc Belleville , Edith Beigné , Christian Bernard
Microelectronics Journal, 2011, 42 (5), pp.718-732. ⟨10.1016/j.mejo.2011.02.005⟩
Journal articles lirmm-00607877v1

On-Chip Process Variability Monitoring Flow

Nabila Moubdi , Philippe Maurine , Robin M. Wilson , Nadine Azemard , Sylvain Engels
Journal of Low Power Electronics, 2010, 6 (4), pp.601-606. ⟨10.1166/jolpe.2010.1109⟩
Journal articles lirmm-00546368v1

Timing Margin Evaluation with a Simple Statistical Timing Analysis Flow

Sylvain Engels , Robin M. Wilson , Nadine Azemard , Philippe Maurine , Vincent Migairou
Journal of Embedded Computing, 2009, 3 (3), pp.221-229. ⟨10.3233/JEC-2009-0094⟩
Journal articles lirmm-00371162v1
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Temperature and Voltage Aware Timing Analysis

Benoit Lasbouygues , Robin P. Wilson , Nadine Azemard , Philippe Maurine
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007, 26 (4), pp.801-815. ⟨10.1109/TCAD.2006.884860⟩
Journal articles lirmm-00178921v1

Logical Effort Model Extension to Propagation Delay Representation

Benoit Lasbouygues , Sylvain Engels , Robin P. Wilson , Philippe Maurine , Nadine Azemard
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25 (9), pp.1677-1684. ⟨10.1109/TCAD.2005.857400⟩
Journal articles lirmm-00104315v1

A Comprehensive Performance Macro-Modeling of on-Chip RC Interconnects Considering Line Shielding Effects

Sylvain Engels , Robin Wilson , Nadine Azemard , Philippe Maurine
Integration, the VLSI Journal, 2006, 39 (4), pp.433-456. ⟨10.1016/j.vlsi.2005.08.007⟩
Journal articles lirmm-00106854v1

Delay Bounds Based Constraint Distribution Method

Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne
IEE Proceedings - Computers and Digital Techniques (1994-2006), 2005, 152 (6), pp.765-770. ⟨10.1049/ip-cdt:20050026⟩
Journal articles lirmm-00105370v1

Transition Time Modeling in Deep Submicron CMOS

Philippe Maurine , Mustapha Rezzoug , Nadine Azemard , Daniel Auvergne
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002, 21 (11), pp.1352-1363. ⟨10.1109/TCAD.2002.804088⟩
Journal articles lirmm-00239324v1

General Representation of CMOS Structure Transition time for Timing Library Representation

Philippe Maurine , Nadine Azemard , Daniel Auvergne
Electronics Letters, 2002, 38 (4), pp.175-177. ⟨10.1049/el:20020103⟩
Journal articles lirmm-00239318v1

POPS: A tool for delay/power performance optimization

Nadine Azemard , Daniel Auvergne
Journal of Systems Architecture, 2001, 47 (3), pp.375-382. ⟨10.1016/S1383-7621(00)00055-2⟩
Journal articles lirmm-00239314v1

Post-Layout Timing Simulation of CMOS Circuits

Denis Deschacht , Michel Robert , Nadine Azemard , Daniel Auvergne
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993, 12 (8), pp.1170-1177. ⟨10.1109/43.238609⟩
Journal articles lirmm-00239206v1

A Performance Driven Layout Synthesis Approach for Digital CMOS Cell Implementation

Michel Robert , Guy Cathébras , Nadine Azemard , Denis Deschacht , Daniel Auvergne
Integration, the VLSI Journal, 1993
Journal articles lirmm-00239254v1

Input Waveform Slope Effects in CMOS Delays

Daniel Auvergne , Nadine Azemard , Denis Deschacht , Michel Robert
IEEE Journal of Solid-State Circuits, 1990, 25 (6), pp.1588-1590. ⟨10.1109/4.62196⟩
Journal articles lirmm-00239201v1

Evaluation Dynamique et Optimisation des Structures CMOS et VLSI

Daniel Auvergne , Nadine Azemard , Guy Cathébras , Denis Deschacht , Michel Robert
Revue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, 1989, 8 (6), pp.593-607
Journal articles lirmm-00239199v1
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Oscillatory Neural Networks for Edge AI Computing

Corentin Delacour , Stefania Carapezzi , Madeleine Abernot , Gabriele Boschetto , Nadine Azemard
ISVLSI 2021 - IEEE Computer Society Annual Symposium on VLSI, Jul 2021, Tampa, United States. pp.326-331, ⟨10.1109/ISVLSI51109.2021.00066⟩
Conference papers lirmm-03229257v1
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Iterative Method for Performance Prediction Improvement of Integrated Circuits

Gwenael Chaillou , Philippe Maurine , Jean-Marc J.-M. Galliere , Nadine Azemard
DCIS 2021 - 36th Conference on Design of Circuits and Integrated Systems, Nov 2021, Vila do Conde, Portugal. pp.1-5, ⟨10.1109/DCIS53048.2021.9666182⟩
Conference papers lirmm-03710383v1
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EU H2020 NEURONN: Two-Dimensional Oscillatory Neural Networks for Energy Efficient Neuromorphic Computing

Aida Todri-Sanial , Stefania Carapezzi , Corentin Delacour , Madeleine Abernot , Eirini Karachristou
EFECS 2020 - European Forum for Electronic Components and Systems, Nov 2020, Brussels, Belgium
Conference papers lirmm-03024126v1
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Stretchable Strain Sensors for Human Movement Monitoring

Abhishek Singh Dahiya , Thierry Gil , Nadine Azemard , Jérôme Thireau , Alain Lacampagne
DTIP 2020 - 22nd Symposium on Design, Test, Integration & Packaging of MEMS and MOEMS, Jun 2020, (Virtual ), France. ⟨10.1109/DTIP51112.2020.9139154⟩
Conference papers hal-02903236v1
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NeurONN: Neuromorphic Computing for Artificial Intelligence at the Edge

Stefania Carapezzi , Madeleine Abernot , Corentin Delacour , Nadine Azemard , Jérémie Salles
3rd AI Compute Symposium (IBM IEEE CAS/EDS), Oct 2020, Zurich (virtual), Switzerland
Conference papers lirmm-03009213v1

Combined analysis of supply voltage and body-bias voltage for energy management

Rida Kheirallah , Jean-Marc J.-M. Galliere , Nadine Azemard , Gilles R. Ducharme
PATMOS: Power And Timing Modeling, Optimization and Simulation, Jul 2018, Platja d’Aro, Spain. pp.88-91, ⟨10.1109/PATMOS.2018.8464159⟩
Conference papers lirmm-01867809v1

Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic

Nicolas Jeanniot , Gaël Pillonnet , Pascal Nouet , Nadine Azemard , Aida Todri-Sanial
ICRC: International Conference on Rebooting Computing, Nov 2017, Washington, DC, United States. ⟨10.1109/ICRC.2017.8123661⟩
Conference papers lirmm-01768831v1
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Atomistic to circuit level modeling of defective doped SWCNTs with contacts for on-chip interconnect application

Jie Liang , Lee Jaehyun , Salim Berrada , Vihar P. Georgiev , Asenov Asen
NMDC: Nanotechnology Materials and Devices Conference, Oct 2017, Singapore, Singapore. pp.66-67, ⟨10.1109/NMDC.2017.8350506⟩
Conference papers lirmm-01880220v1
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Physical description and analysis of doped carbon nanotube interconnects

Jie Liang , Liuyang Zhang , Nadine Azemard , Pascal Nouet , Aida Todri-Sanial
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2016, Brême, Germany. pp.250-255, ⟨10.1109/PATMOS.2016.7833695⟩
Conference papers lirmm-01457338v1

Statistical Energy Study for 28nm FDSOI Technology

Rida Kheirallah , Gilles R. Ducharme , Nadine Azemard
VARI: Workshop on CMOS Variability, Sep 2015, Salvador, Bahia, Brazil
Conference papers lirmm-01256280v1

Statistical Energy Study for 28nm FDSOI Devices

Rida Kheirallah , Jean-Marc J.-M. Galliere , Aida Todri-Sanial , Gilles R. Ducharme , Nadine Azemard
EuroSimE: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, Apr 2015, Budapest, Hungary. ⟨10.1109/EuroSimE.2015.7103149⟩
Conference papers lirmm-01168602v1

VARI Worshop Overview

Nadine Azemard
DCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.159-161
Conference papers lirmm-00762113v1

Statistical Cells Timing Metrics Characterization

Nadine Azemard , Zeqin Wu , Philippe Maurine , Gilles R. Ducharme
FTFC: Faible Tension - Faible Consommation, Jun 2012, Paris, France
Conference papers lirmm-00762131v1

Statistical Timing Characterization of Standard Cells with Semi-Monte-Carlo Method

Nadine Azemard , Zeqin Wu , Philippe Maurine , Gilles R. Ducharme
VARI: Workshop on CMOS Variaility, May 2011, Grenoble, France
Conference papers lirmm-00617593v1

Characterizing Statistical Cells Timing Metrics with Semi-Monte-Carlo Method

Nadine Azemard , Zeqin Wu , Philippe Maurine , Gilles R. Ducharme
VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2011, Hong-Kong, China
Conference papers lirmm-00617606v1

Voltage Scaling and Body Biasing Methodology for High Performance Hardwired LDPC

Nabila Moubdi , Philippe Maurine , Nadine Azemard , Robin M. Wilson , Sylvain Engels
ICICDT: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.82-85, ⟨10.1109/ICICDT.2010.5510289⟩
Conference papers lirmm-00546316v1

Computing Delay Correlations in SSTA

Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme
ICICDT: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.130-133, ⟨10.1109/ICICDT.2010.5510277⟩
Conference papers lirmm-00546301v1

SSTA with Cell-to-Cell Delay Correlations

Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme
VARI: Workshop on CMOS Variability, May 2010, Montpellier, France
Conference papers lirmm-00546322v1

SSTA with Delay Correlations

Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme
NEWCAS: New Circuits and Systems, Jun 2010, Montreal, QC, Canada. pp.261-266, ⟨10.1109/NEWCAS.2010.5603930⟩
Conference papers lirmm-00504882v1

On-Chip Process Variability Monitoring

Nabila Moubdi , Philippe Maurine , Robin M. Wilson , Nadine Azemard , Vincent Dumettier
VARI: Workshop on CMOS Variability, May 2010, Montpellier, France
Conference papers lirmm-00546337v1
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Product On-Chip Process Compensation for Low Power and Yield Enhancement

Nabila Moubdi , Philippe Maurine , Robin M. Wilson , Nadine Azemard , Vincent Dumettier
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.247-255, ⟨10.1007/978-3-642-11802-9_29⟩
Conference papers lirmm-00433504v1
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Un nouveau système d'instrumentation en ligne pour la caractérisation et l'adaptation dynamique aux variations

Bettina Rebaud , Marc Belleville , Edith Beigné , Michel Robert , Philippe Maurine
FTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Suisse
Conference papers lirmm-00404810v1
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Digital Timing Slack Monitors and their Specific Insertion Flow for Adaptive Compensation of Variabilities

Bettina Rebaud , Marc Belleville , Edith Beigné , Christian Bernard , Michel Robert
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.266-275, ⟨10.1007/978-3-642-11802-9_31⟩
Conference papers lirmm-00433462v1

On-Chip Process Variability Monitoring

Nabila Moubdi , Robin M. Wilson , Sylvain Engels , Nadine Azemard , Philippe Maurine
DATE: Design, Automation and Test in Europe, Apr 2009, Nice, France
Conference papers lirmm-00374368v1

An Innovative Timing Slack Monitor for Variation Tolerant Circuits

Bettina Rebaud , Marc Belleville , Edith Beigné , Michel Robert , Philippe Maurine
ICICDT: International Conference on IC Design & Technology, May 2009, Austin, TX, United States. pp.215-218, ⟨10.1109/ICICDT.2009.5166299⟩
Conference papers lirmm-00371174v1
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Interpreting SSTA Results with Correlation

Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2009, Delft, Netherlands. pp.16-25, ⟨10.1007/978-3-642-11802-9_6⟩
Conference papers lirmm-00433505v1

On-Chip Timing Slack Monitoring

Bettina Rebaud , Marc Belleville , Edith Beigné , Michel Robert , Philippe Maurine
VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2009, Florianopolis, Brazil. pp.89-94, ⟨10.1109/VLSISOC.2009.6041336⟩
Conference papers lirmm-00429350v1

Interpretation of SSTA Results

Zeqin Wu , Nadine Azemard , Philippe Maurine , Gilles R. Ducharme
FTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Switzerland
Conference papers lirmm-00374060v1
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Étude des violations de temps d'établissement et de maintien dues aux variations du processus de fabrication dans un opérateur arithmétique

Bettina Rebaud , Zeqin Wu , Marc Belleville , Christian Bernard , Michel Robert
JNRDM 2008 - 11e Journées Nationales du Réseau Doctoral de Microélectronique, May 2008, Bordeaux, France
Conference papers lirmm-00281175v2

Conditional Moments based SSTA Considering Switching Process Induced Correlations

Zeqin Wu , Philippe Maurine , Gilles R. Ducharme , Nadine Azemard
DCIS: Design of Circuits and Integrated Systems, Nov 2008, Grenoble, France. pp.70-77
Conference papers lirmm-00340221v1
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Impact de la variabilité des caractéristiques temporelles des cellules combinatoires et séquentielles sur un opérateur numérique

Bettina Rebaud , Marc Belleville , Christian Bernard , Zeqin Wu , Michel Robert
FTFC: Faible Tension - Faible Consommation, May 2008, Louvain-La-Neuve, Belgique
Conference papers lirmm-00283731v1

SSTA Considering Effects of Structure Correlations, Input Slope and Output Load Variations

Zeqin Wu , Philippe Maurine , Gilles R. Ducharme , Nadine Azemard
FTFC: Faible Tension - Faible Consommation, May 2008, Louvain-la-Neuve, Belgium. pp.39-43
Conference papers lirmm-00288537v1
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A Comparative Study of Variability Impact on Static Flip-Flop Timing Characteristics

Bettina Rebaud , Marc Belleville , Christian Bernard , Michel Robert , Patrick Maurine
ICICDT: International Conference on IC Design and Technology, Jun 2008, Grenoble, France. pp.167-170
Conference papers lirmm-00305246v1

SSTA with Structure Correlations Considering input Slope and Output Load Variations

Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme
GDR SOC-SIP, Jun 2008, Paris, France. pp.3
Conference papers lirmm-00340231v1

SSTA Considering Switching Process Induced Correlations

Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme
APCCAS: Asia Pacific Conference on Circuits and System, Nov 2008, Macao, China. pp.562-565, ⟨10.1109/APCCAS.2008.4746085⟩
Conference papers lirmm-00340564v1

Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier

Bettina Rebaud , Marc Belleville , Christian Bernard , Zeqin Wu , Michel Robert
ISVLSI: International Symposium on Very Large Scale Integration, Apr 2008, Montpellier, France. pp.316-321, ⟨10.1109/ISVLSI.2008.70⟩
Conference papers lirmm-00280809v1

SSTA with Correlations Considering input Slope and Output Load Variations

Zeqin Wu , Philippe Maurine , Nadine Azemard , Gilles R. Ducharme
VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2008, Rhodes Island, Greece. pp.164-167
Conference papers lirmm-00332757v1

A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation

Vincent Migairou , Robin Wilson , Sylvain Engels , Zeqin Wu , Nadine Azemard
FTFC: Faible Tension - Faible Consommation, May 2007, Paris, France. pp.19-25
Conference papers lirmm-00178454v1

Une Famille d'Additionneurs Asynchrones CMOS Bundled Data à Temps de Calcul Dépendant aux Données

Robin Perrot , Nadine Azemard , Philippe Maurine
FTFC: Faible Tension - Faible Consommation, May 2007, Paris, France. pp.75-80
Conference papers lirmm-00178466v1

A Simple Statistical Timing Analysis Flow and its Application to Timing Margin Evaluation

Vincent Migairou , Robin Wilson , Sylvain Engels , Zeqin Wu , Nadine Azemard
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden. pp.138-147, ⟨10.1007/978-3-540-74442-9_14⟩
Conference papers lirmm-00175076v1

Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops

Benoit Lasbouygues , Robin M. Wilson , Nadine Azemard , Philippe Maurine
DATE: Design, Automation and Test in Europe, Mar 2007, Nice, France. ⟨10.1109/DATE.2007.364426⟩
Conference papers lirmm-00178525v1

Request-Skip Adders: CMOS Standard Cell Data Dependent Adders

Robin Perrot , Nadine Azemard , Philippe Maurine
ICECS: International Conference on Electronics, Circuits and Systems, Dec 2006, Nice, France. pp.510-513, ⟨10.1109/ICECS.2006.379837⟩
Conference papers lirmm-00130195v1

Circuit Performance Optimization under Delay Constraints

Alexandre Verle , Alexis Landrault , Philippe Maurine , Nadine Azemard
DCIS: Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain
Conference papers lirmm-00117119v1

Exploration of the Area-Latency Tradeoff of Asynchronous CMOS data Dependent Adders

Robin Perrot , Philippe Maurine , Nadine Azemard
DCIS: Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain
Conference papers lirmm-00117102v1

Timing Analysis in Presence of Voltage Drops and Temperature Gradients

Benoit Lasbouygues , Robin M. Wilson , Nadine Azemard , Philippe Maurine
TAU: Timing Issues in the Specification and Synthesis of Digital Systems, Feb 2006, San Jose, CA, United States. pp.28-34
Conference papers lirmm-00106705v1

Timing Analysis in Presence of Supply Voltage and Temperature Variations

Benoit Lasbouygues , Robin M. Wilson , Nadine Azemard , Philippe Maurine
ISPD: International Symposium on Physical Design, Apr 2006, San Jose, CA, United States. pp.10-16, ⟨10.1145/1123008.1123012⟩
Conference papers lirmm-00102760v1

Circuit Sizing Method under Delay Constraint

Alexandre Verle , Alexis Landrault , Philippe Maurine , Nadine Azemard
ISCAS: International Symposium on Circuits and Systems, May 2006, Island of Kos, Greece. pp.5123-5126, ⟨10.1109/ISCAS.2006.1693785⟩
Conference papers lirmm-00106911v1
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Statistical Characterization of Library Timing Performance

Vincent Migairou , Robin P. Wilson , Sylvain Engels , Nadine Azemard , Philippe Maurine
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2006, Montpellier, France. pp.468-476, ⟨10.1007/11847083_45⟩
Conference papers lirmm-00093233v1
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Une Famille d'Additionneur Asynchrones CMOS à Temps de Calcul Dépendant de Données

Robin Perrot , Nadine Azemard , Philippe Maurine
JNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France. pp.469-472
Conference papers lirmm-00102842v1

Circuit Optimization Based on Speed Indicators

Alexandre Verle , Alexis Landrault , Philippe Maurine , Nadine Azemard
ICECS: International Conference on Electronics, Circuits and Systems, Dec 2005, Gammarth, Tunisia. pp.167-170, ⟨10.1109/icecs.2005.4633585⟩
Conference papers lirmm-00106439v1

Additionneurs RCA Data Dependent Micropipelines

Robin Perrot , Nadine Azemard , Philippe Maurine
FTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.183-188
Conference papers lirmm-00106005v1
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Low Power Oriented CMOS Circuit Optimization Protocol

Alexandre Verle , Xavier Michel , Nadine Azemard , Philippe Maurine , Daniel Auvergne
DATE 2005 - 8th Design, Automation and Test in Europe Conference and Exhibition, Mar 2005, Munich, Germany. pp.640-645, ⟨10.1109/DATE.2005.202⟩
Conference papers lirmm-00106452v1

Ripple Carry Adder for Micropipeline Circuits

Robin Perrot , Nadine Azemard , Philippe Maurine
DCIS 2005 - 20th Conference on Design of Circuits and Integrated Systems, Nov 2005, Lisbonne, Portugal
Conference papers lirmm-00106075v1
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Speed Indicators for Circuit Optimization

Alexandre Verle , Alexis Landrault , Philippe Maurine , Nadine Azemard
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.618-628, ⟨10.1007/11556930_63⟩
Conference papers lirmm-00106076v1

Protocole d'Optimisation de Circuit CMOS Orienté Basse Puissance

Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard
FTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.17-22
Conference papers lirmm-00106002v1

Synthèse Physique et Optimisation des Performances au Niveau Transistor

Alexis Landrault , Alexandre Verle , Philippe Maurine , Nadine Azemard
FTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.91-95
Conference papers lirmm-00106004v1

Path Optimization Protocol Based on Speed Low Power Metrics

Alexandre Verle , Alexis Landrault , Philippe Maurine , Nadine Azemard
EUROCON: International Conference on "Computer as a Tool", Nov 2005, Belgrade, Serbia. pp.523-526, ⟨10.1109/EURCON.2005.1629980⟩
Conference papers lirmm-00106428v1
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Temperature Dependency in UDSM Process

Benoit Lasbouygues , Robin M. Wilson , Philippe Maurine , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.693-703, ⟨10.1007/11556930_71⟩
Conference papers lirmm-00106077v1

Optimization Protocol Based on Low Power Metrics

Alexandre Verle , Alexis Landrault , Philippe Maurine , Nadine Azemard
IWLS: International Workshop on Logic Synthesis, Jun 2005, Lake Arrowhead Resort, CA, United States. pp.288-293
Conference papers lirmm-00106018v1
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Definition of P/N Width Ratio for CMOS Standard Cell Library

Alexandre Verle , Philippe Maurine , Nadine Azemard , Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.769-773
Conference papers lirmm-00108933v1
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RC on-chip interconnect Performance revisited

Philippe Maurine , Nadine Azemard , Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.809-814
Conference papers lirmm-00108934v1
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Physical Extension of the Logical Effort Model

Benoit Lasbouygues , Robin M. Wilson , Philippe Maurine , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.838-848, ⟨10.1007/978-3-540-30205-6_86⟩
Conference papers lirmm-00108895v1
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Temperature Dependence in Low Power CMOS UDSM Process

Benoit Lasbouygues , Robin M. Wilson , Philippe Maurine , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.111-118, ⟨10.1007/978-3-540-30205-6_13⟩
Conference papers lirmm-00108893v1
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Performance Metric Based Optimization Protocol

Xavier Michel , Alexandre Verle , Philippe Maurine , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.100-109, ⟨10.1007/978-3-540-30205-6_12⟩
Conference papers lirmm-00108892v1

Automatic Layout Synthesis Based Performance Optimization

Alexis Landrault , Nadine Azemard , Philippe Maurine , Michel Robert , Daniel Auvergne
IWLS: International Workshop on Logic Synthesis, Jun 2004, Temecula, CA, United States. pp.80-85
Conference papers lirmm-00108654v1
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Optimization Protocol Based on Performance Metric

Xavier Michel , Alexandre Verle , Nadine Azemard , Philippe Maurine , Daniel Auvergne
DCIS 2004 - 19th International Conference on Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.964-968
Conference papers lirmm-00108935v1
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Delay Bound Based CMOS Gate Sizing Technique

Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne
ISCAS: International Symposium on Circuits and Systems, May 2004, Vancouver, BC, Canada. pp.189-192, ⟨10.1109/ISCAS.2004.1329494⟩
Conference papers lirmm-00108856v1
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Design Optimization with Automated Cell Generation

Alexis Landrault , Nadine Azemard , Philippe Maurine , Michel Robert , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2004, Santorini, Greece. pp.722-731, ⟨10.1007/978-3-540-30205-6_74⟩
Conference papers lirmm-00108894v1

Timing Performance Representation of a CMOS Standard Cell Library

Benoit Lasbouygues , J. Schindler , Sylvain Engels , Philippe Maurine , Xavier Michel
DCIS: Design of Circuits and Integrated Systems, Nov 2003, Ciudad Real, Spain. pp.83-88
Conference papers lirmm-00239460v1

Metric Definition for Circuit Speed Optimization

Xavier Michel , Alexandre Verle , Nadine Azemard , Philippe Maurine , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2003, Turin, Italy. pp.451-460
Conference papers lirmm-00269568v1

Metric Definition for Circuit Speed Optimization

Xavier Michel , Alexandre Verle , Philippe Maurine , Nadine Azemard , Daniel Auvergne
IWLS: International Workshop on Logic Synthesis, May 2003, Laguna Beach, CA, United States
Conference papers lirmm-00269689v1
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CMOS Gate Sizing under Delay Constraint

Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2003, Torino, Italy. pp.60-69, ⟨10.1007/978-3-540-39762-5_8⟩
Conference papers lirmm-00244021v1
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Dimensionnement de Portes CMOS Sous Contrainte de Délai

Alexandre Verle , Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne
FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.111-117
Conference papers lirmm-00269522v1
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Continuous Representation of the Performance of a CMOS Library

Benoit Lasbouygues , J. Schindler , Sylvain Engels , Philippe Maurine , Xavier Michel
ESSCIRC: European Solid-State Circuits Conference, Sep 2003, Estoril, Portugal. pp.595-598, ⟨10.1109/ESSCIRC.2003.1257205⟩
Conference papers lirmm-00239459v1
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Définition d'une Métrique d'Insertion de Buffers

Xavier Michel , Alexandre Verle , Nadine Azemard , Philippe Maurine , Daniel Auvergne
FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.131-136
Conference papers lirmm-00269520v1
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Représentation Unifiée des Performances Temporelles d'une Bibliothèque de Cellules Standards

Benoit Lasbouygues , J. Schindler , Sylvain Engels , Philippe Maurine , Nadine Azemard
FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.119-124
Conference papers lirmm-00269519v1

Metric Definition for Buffer Insertion

Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 2002, Santander, Spain. pp.307-312
Conference papers lirmm-00239458v1
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Evaluation et Optimisation de Chemins Combinatoires

Xavier Michel , Philippe Maurine , Nadine Azemard , Daniel Auvergne
Colloque du GDR CAO de Circuits et Systèmes Intégrés, May 2002, Paris, France. pp.173-176
Conference papers lirmm-00269329v1

Defining the Maximum Speed of CMOS Gate Library

Philippe Maurine , Nadine Azemard , Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 2002, Santander, Spain. pp.81-86
Conference papers lirmm-00239455v1
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Structure Independent Representation of Output Transition Time for CMOS Library

Philippe Maurine , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2002, Seville, Spain. pp.247-257, ⟨10.1007/3-540-45716-X_25⟩
Conference papers lirmm-00244012v1

Gate Speed Improvement at Minimal Power Dissipation

Philippe Maurine , Xavier Michel , Nadine Azemard , Daniel Auvergne
APPCAS: Asia-Pacific Conference on Circuits and Systems, Oct 2002, Denpasar, Bali, pp.278-282
Conference papers lirmm-00239453v1

Full Analyttical Model for delay Performance Estimation in Submicron CMOS

Philippe Maurine , Nadine Azemard , Daniel Auvergne
MIXDES: Mixed Design of Integrated Circuits and Systems, Jun 2001, Zakopane, Poland. pp.355-359
Conference papers lirmm-00239444v1

Performance Indicators for Designing CMOS Logic

Philippe Maurine , Nadine Azemard , Daniel Auvergne
ICM: International Conference on Microelectronics, Oct 2001, Rabat, Morocco. pp.99-102, ⟨10.1109/ICM.2001.997497⟩
Conference papers lirmm-00239446v1

Technological Assignment for a Minimal Power Consumption

Philippe Maurine , Nadine Azemard , Daniel Auvergne
VLSI-SoC: Very Large Scale Integration - System-on-Chip, Dec 2001, Montpellier, France. pp.236-241
Conference papers lirmm-00239450v1

Timing Closure Management based on Delay Bound Determination

Nadine Azemard , Michel Aline , Philippe Maurine , Daniel Auvergne
VLSI-SoC: Very Large Scale Integration - System-on-Chip, Dec 2001, Montpellier, France. pp.430-434
Conference papers lirmm-00239452v1

Switching Current Modeling in CMOS Inverter for Speed and Power Estimation

Philippe Maurine , Régis Poirier , Nadine Azemard , Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 2001, Porto, Portugal. pp.618-622
Conference papers lirmm-00239448v1

Delay Bound Determination for Timing Closure Satisfaction

Nadine Azemard , Michel Aline , Daniel Auvergne
ISCAS: International Symposium on Circuits and Systems, May 2001, Sydney, NSW, Australia. pp.375-378, ⟨10.1109/ISCAS.2001.922063⟩
Conference papers lirmm-00241322v1
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Deep Submicron Switching Current Modeling for CMOS Logic Output Transition Time Determination

Philippe Maurine , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2001, Yverdon-Les-Bains, Switzerland. pp.5.3.1-5.3.10
Conference papers lirmm-00244010v1

Delay Bound Determination for Timing Closure on CMOS Circuits

Nadine Azemard , Michel Aline , Philippe Maurine , Daniel Auvergne
IWLS: International Workshop on Logic and Synthesis, Jun 2001, Granlibakken Conference Center, United States. pp.96-100
Conference papers lirmm-00244007v1

POPS: A tool for Delay/Power Performance/Optimization

Nadine Azemard , Michel Aline , Daniel Auvergne
ASIC-SoC: International ASIC/SOC Conference, Sep 2000, Arlington, VA, United States. pp.276-280, ⟨10.1109/ASIC.2000.880715⟩
Conference papers lirmm-00239434v1

Upper and Lower bound Determination of delay on Critical Path

Michel Aline , Nadine Azemard , Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 2000, Montpellier, France. pp.543-547
Conference papers lirmm-00239437v1

Delay Bound Determination for Path Constraint Satisfaction

Nadine Azemard , Michel Aline , Daniel Auvergne
ISMA: International Symposium on Microelectronics and Assembly, Nov 2000, Singapour, China. pp.122-129, ⟨10.1117/12.405403⟩
Conference papers lirmm-00241266v1
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A Physical Synthesis Design Flow based on Virtual Components

Fernando Gehm Moraes , Michel Robert , Daniel Auvergne , Nadine Azemard
DCIS: Design of Circuits and Integrated Systems, Nov 2000, Montpellier, France. pp.740-745
Conference papers lirmm-00239439v1

Local Gate Resizing for Critical Path Optimization

Nadine Azemard , Michel Aline , Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 1999, Palma de Majorque, Spain. pp.195-200
Conference papers lirmm-00239429v1

Satisfaction of Delay/Power Constraints by Iterative Gate Sizing

Nadine Azemard , Michel Aline , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1999, Kos, Greece. pp.325-334
Conference papers lirmm-00244003v1

Post Layout Management of Delay Power Constraints in Submicronic CMOS Implementation

Nadine Azemard , Michel Aline , Daniel Auvergne
IWLS: International Workshop on Logic Synthesis, Jun 1999, Lake Tahoe, CA, United States. pp.198-201
Conference papers lirmm-00244002v1

Delay-Power Performance Analysis

Séverine Cremoux , Michel Aline , Nadine Azemard , Daniel Auvergne
ICECS: International Conference on Electronics, Circuits and Systems, Sep 1999, Pafos, Cyprus. pp.1543-1546, ⟨10.1109/ICECS.1999.814465⟩
Conference papers lirmm-00239424v1

A New Tool for Path Performance Optimization

Séverine Cremoux , Nadine Azemard , Michel Aline , Daniel Auvergne
International Workshop on IP Based Synthesis and System Design, Dec 1998, Grenoble, France. pp.175-179
Conference papers lirmm-00241408v1

POPS: A New Tool for Path Evaluation

Séverine Cremoux , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1998, Lyngby, Denmark. pp.235-244
Conference papers lirmm-00241378v1

Path Selection for Delay and Power Performance Optimization

Séverine Cremoux , Nadine Azemard , Daniel Auvergne
SAME: Sophia Antipolis Forum on Microelectronics, Oct 1998, Sophia Antipolis, France. pp.48-53
Conference papers lirmm-00239415v1

POPS: Performance Optimization by Path Selection

Séverine Cremoux , Nadine Azemard , Michel Aline , Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 1998, Madrid, Spain. pp.10-15
Conference papers lirmm-00239421v1

Long and Short Path Sizing for Delay-Power Performance Management

Séverine Cremoux , Nadine Azemard , Daniel Auvergne
IWLS: International Workshop on Logic Synthesis, Jun 1998, Lake Tahoe, CA, United States
Conference papers lirmm-00241376v1

Path Resizing Based on Incremental Technique

Séverine Cremoux , Nadine Azemard , Daniel Auvergne
ISCAS: International Symposium on Circuits and Systems, May 1998, Monterey, CA, United States. pp.90-93, ⟨10.1109/ISCAS.1998.705219⟩
Conference papers lirmm-00241190v1

Path Sensitization for Performance Optimization

Séverine Cremoux , Jose Luis Guntzel , Nadine Azemard , Daniel Auvergne
MIXDES: Mixed Design of Integrated Circuits and Systems, Jun 1997, Poznan, Poland. pp.195-200
Conference papers lirmm-00239409v1

Performance Otimization by Path Selection

Séverine Cremoux , Thierry Monnier , Nadine Azemard , Daniel Auvergne
IWLS: International Workshop on Logic Synthesis, May 1997, Tahoe City, CA, United States. pp.152-155
Conference papers lirmm-00241372v1

Selective Gate Sizing for Delay/Power Performance Management

Séverine Cremoux , Nadine Azemard , Daniel Auvergne
IWLAS: International Workshop on Logic and Architecture Synthesis, Dec 1997, Grenoble, France
Conference papers lirmm-00241374v1

A Path Sensitization Approach for Performance Optimization

Thierry Monnier , Séverine Cremoux , Nadine Azemard , Daniel Auvergne
ISIC: International Symposium on IC Technology, Systems and Applications, Sep 1997, Singapore, China. pp.94-97
Conference papers lirmm-00241160v1
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Design and Selection of Buffers for Minimum Power-Delay Product

Sandra Turgis , Nadine Azemard , Daniel Auvergne
ED&TC: European Design and Test Conference, Mar 1996, Paris, France. pp.224-228, ⟨10.1109/EDTC.1996.494153⟩
Conference papers lirmm-00239400v1

A Path Selection Algorithm for Performance Optimization

Séverine Cremoux , Thierry Monnier , Jose Luis Guntzel , Nadine Azemard , Daniel Auvergne
IWLAS: International Workshop on Logic and Architecture Synthesis, Dec 1996, Grenoble, France. pp.277-284
Conference papers lirmm-00241369v1

Design and Sizing of Tapered Buffers for Minimum Power-Delay Product

Sandra Turgis , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1995, Oldenburg, Germany. pp.79-90
Conference papers lirmm-00241366v1

Short-Circuit Power Dissipation calculation on CMOS Inverters using the Equivalent Short-Circuit Capacitance Concept

Sandra Turgis , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1995, Oldenburg, Germany. pp.213-224
Conference papers lirmm-00241367v1
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Explicit Evaluation of Short Circuit Power Dissipation for CMOS Logic Structures

Sandra Turgis , Nadine Azemard , Daniel Auvergne
ISLPD: International Symposium on Low Power Design, Apr 1995, Dana Point, CA, United States. pp.129-134, ⟨10.1145/224081.224104⟩
Conference papers lirmm-00241153v1

Standard Cell Performance Modelling

Myrian Mellah , Nadine Azemard , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1994, Barcelone, Spain. pp.158-167
Conference papers lirmm-00241364v1

General Determination of Buffer Insertion Limits

Myrian Mellah , Nadine Azemard , Daniel Auvergne
IWoDA: International Workshop on Design Automation, Jun 1994, Moscou, Russia. pp.21-23
Conference papers lirmm-00241361v1

Tool Box for Performance Driven Macrocell layout Synthesis

Fernando Gehm Moraes , Nadine Azemard , Michel Robert , Daniel Auvergne
Eurochip Workshop on VLSI Design Training, Sep 1993, Toledo, Spain. pp.56-61
Conference papers lirmm-00241348v1

Flexible Macrocell layout Generator

Fernando Gehm Moraes , Nadine Azemard , Michel Robert , Daniel Auvergne
4th ACM/SIGDA Physical Design Workshop, Layout Synthesis for the New Generation of VLSI ASIC Technologies, Apr 1993, UCLA Conference Center, CA, USA, pp.105-116
Conference papers lirmm-00241344v1

Evaluation of Speed up Strategy from Gate Performance Modelling

Daniel Auvergne , Sylvie Amat , Myrian Mellah , Nadine Azemard , Michel Robert
IFIP Workshop on Logic and Architecture Synthesis, Dec 1993, Grenoble, France, pp.193-208
Conference papers lirmm-00241358v1

A Real Characterization based Buffer Selection Algorithm

Nadine Azemard , Sylvie Amat , Myrian Mellah , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1993, La Grande Motte, France
Conference papers lirmm-00241350v1
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P.SIZE: A Sizing aid for Optimized Designs

Nadine Azemard , Vincent Bonzom , Daniel Auvergne
EURODAC 1992 - European Design Automation Conference, Sep 1992, Hamburg, Germany. pp.160-166, ⟨10.1109/EURDAC.1992.246248⟩
Conference papers lirmm-00239396v1
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Optimization Technique for Performance driven Cell Generator

Nadine Azemard , Vincent Bonzom , Sylvie Amat , Daniel Auvergne
EuroASIC 1992 - European Conference on Application Specific Integrated Circuits, Jun 1992, Paris, France. pp.152-155, ⟨10.1109/EUASIC.1992.228032⟩
Conference papers lirmm-00239390v1

Application of Explicit Delay Time Modelling to CMOS Data Path Evaluation and Transistor Sising

Nadine Azemard , Denis Deschacht , Michel Robert , Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 1992, Paris, France. pp.102-108
Conference papers lirmm-00241327v1
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Evaluation of VLSI Layout Implementation for Efficiency

Michel Robert , Joel Trauchessec , Guy Cathébras , Vincent Bonzom , Nadine Azemard
EURO-ASIC 1991 - European Conference on Design Automation with European Event in ASIC Design, May 1991, Paris, France. pp.362-365, ⟨10.1109/EUASIC.1991.212836⟩
Conference papers lirmm-00239384v1

An Accurate and Efficient Delay Time Modelling and its Application to CMOS Data Path Evaluation and Transistor Sizing

Daniel Auvergne , Nadine Azemard , Denis Deschacht , Michel Robert
World Congress on Computation and Applied Mathematics, IMACS: International Association for Mathematics and Computers in Simulation, Jul 1991, Dublin, Ireland. pp.1661-1663
Conference papers lirmm-00239387v1
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Formal Sizing Rules of CMOS Circuits

Daniel Auvergne , Nadine Azemard , Vincent Bonzom , Denis Deschacht , Michel Robert
EDAC 1991 - European Conference on Design Automation, Feb 1991, Amsterdam, Netherlands. pp.96-100, ⟨10.1109/EDAC.1991.206368⟩
Conference papers lirmm-00239374v1

CMOS Circuit Speed Optimization based on Closed form Equation

Nadine Azemard , Vincent Bonzom
International Students Microelectronic Conference, May 1990, Zagreb, Yugoslavia, pp.29-32
Conference papers lirmm-00239369v1

Digital Oscillatory Neural Networks for AI Edge Applications

Madeleine Abernot , Nadine Azemard , Aida Todri-Sanial
17e Colloque National du GDR SoC², Jun 2023, Lyon, France
Conference poster hal-04129966v1
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Digital Oscillatory Neural Networks for AI Edge Applications

Madeleine Abernot , Corentin Delacour , Gabriele Boschetto , Stefania Carapezzi , Thierry Gil
16e Colloque National du GDR SoC², Jun 2022, Strasbourg, France.
Conference poster lirmm-03737606v1
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Méthode Itérative pour l’Amélioration de la Prédiction des Performances des Circuits Intégrés

Gwenael Chaillou , Philippe Maurine , Jean-Marc J.-M. Galliere , Nadine Azemard
15e Colloque National du GDR SoC², Jun 2021, Rennes, France
Conference poster lirmm-03358670v1

Mobile Robot Obstacle Avoidance with Oscillatory Neural Networks on FPGA

Madeleine Abernot , Thierry Gil , Corentin Delacour , Gabriele Boschetto , Stefania Carapezzi
IBM-IEEE AI Compute Symposium, Oct 2021, Virtual, France
Conference poster lirmm-03361187v1
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EU H2020 NeurONN: Two-Dimensional Oscillatory Neural Networks for Energy Efficient Neuromorphic Computing

Aida Todri-Sanial , Thierry Gil , Nadine Azemard , Jérémie Salles , Eirini Karachristou
EuroNanoForum 2021, May 2021, Braga, Portugal
Conference poster hal-03364335v1

SmartVista: Smart Autonomous Multi Modal Sensors for Vital Signs Monitoring

Abhishek Singh Dahiya , Benoît Charlot , Marwa Dhifallah , Thierry Gil , Nadine Azemard
Workshop on ‘Smart Bioelectronic and Wearable Systems’, Oct 2019, Brussels, Belgium. , 2019
Conference poster lirmm-02387949v1

Piezoelectric Sensors Based on 1D/2D Materials for Smart Health Monitoring IoT

Marwa Dhifallah , Jie Liang , Thierry Gil , Nadine Azemard , Benoît Charlot
13e Colloque National du GDR SoC², Jun 2019, Montpellier, France. , 2019
Conference poster lirmm-02132507v1

Statistical Timing Characterization

Nadine Azemard , Zeqin Wu , Philippe Maurine , Gilles R. Ducharme
SoC: System on Chip, Oct 2012, Tampere, Finland. International Symposium on System on Chip, 2012, ⟨10.1109/ISSoC.2012.6376360⟩
Conference poster lirmm-00762107v1

Selected Peer-Reviewed Articles from the 4th European Workshop on CMOS Variability, Karlsruhe, Germany, September 9–11, 2013

Nadine Azemard , Jörg Henkel
Nadine Azemard; Jörg Henkel. 10 (1), pp.116-117, 2014, Journal of Low Power Electronics - JOLPE, ⟨10.1166/jolpe.2014.1310⟩
Books lirmm-01168100v1

Selected Articles from the VARI 2011 Workshop

Nadine Azemard , Marc Belleville
Nadine Azemard; Marc Belleville. American Scientific Publishers, 8 (1), pp.82-82, 2012, Special Issue in Journal of Low Power Electronics, ⟨10.1166/jolpe.2012.1178⟩
Books lirmm-00762096v1

Selected Articles from the VARI 2012 Workshop

Nadine Azemard , Gilles Jacquemod
Nadine Azemard; Gilles Jacquemod. American Scientific Publishers, 8 (5), pp.696-696, 2012, Special Issue in Journal of Low Power Electronics, ⟨10.1166/jolpe.2012.1227⟩
Books lirmm-01398764v1

Spécial Issue in Journal of Low Power Electronics

Nadine Azemard
4(3), pp.696-724, 2012
Books lirmm-00546355v1

Special Issue: Power and Timing Modeling, Optimization and Simulation

Nadine Azemard , Lars Svensson
N. Azémard and L. Svensson. IOS Press, Journal of Embedded Computing (JEC), 3(3), pp.155-254, 2009
Books lirmm-00371166v1

Integration, the VLSI Journal

Nadine Azemard , Philippe Maurine , Johan Vounckx
Elsevier, 41 (1), 160 p., 2008, Power and Timing Modeling, Optimization and Simulation (Special Issue), ⟨10.1016/j.vlsi.2007.06.004⟩
Books lirmm-00189961v1

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Nadine Azemard , Lars Svensson
Springer, LNCS (4644), 583 p., 2007, 978-3-540-74442-9. ⟨10.1007/978-3-540-74442-9⟩
Books lirmm-00175210v1

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Johan Vounckx , Nadine Azemard , Philippe Maurine
Springer, LNCS (4148), 677 p., 2006, 978-3-540-39097-8. ⟨10.1007/11847083⟩
Books lirmm-00135046v1
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Towards Autonomous Scalable Integrated Systems

Pascal Benoit , Gilles Sassatelli , Philippe Maurine , Lionel Torres , Nadine Azemard
Design Technology for Heterogeneous Embedded Systems, Springer, pp.63-89, 2012, 978-94-007-1124-2. ⟨10.1007/978-94-007-1125-9_4⟩
Book sections lirmm-01399454v1

Modeling for Designing in Deep Sub-Micron Technologies

Daniel Auvergne , Philippe Maurine , Nadine Azemard
PIGUET C. Low-Power Electronics Design, CPR Press, 2004, 0-8493-1941-2
Book sections lirmm-00109162v1
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Gate Sizing for Low Power Design

Philippe Maurine , Nadine Azemard , Daniel Auvergne
SOC Design Methodologies, 90, Kluwer Academic Publishers, pp.301-312, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_26⟩
Book sections lirmm-00239359v1
Image document

Feasible delay Bound Definition

Nadine Azemard , Michel Aline , Philippe Maurine , Daniel Auvergne
SOC Design Methodologies, 90, Kluwer Academic Publishers, pp.325-335, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_40⟩
Book sections lirmm-00239363v1

Path Selection Based on Incremental Technique

Séverine Cremoux , Nadine Azemard , Daniel Auvergne
Mixed Design of Integrated Circuits and Systems, Kluwer Academic Publishers, pp.137-142, 1998
Book sections lirmm-00239354v1