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Oscillatory Neural Networks for Edge AI Computing
Corentin Delacour
,
Stefania Carapezzi
,
Madeleine Abernot
,
Gabriele Boschetto
,
Nadine Azemard
et al.
Communication dans un congrès
lirmm-03229257
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Iterative Method for Performance Prediction Improvement of Integrated Circuits
Gwenaël Chaillou
,
Philippe Maurine
,
Jean-Marc J.-M. Galliere
,
Nadine Azemard
Communication dans un congrès
lirmm-03710383
v1
|
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Stretchable Strain Sensors for Human Movement Monitoring
Abhishek Singh Dahiya
,
Thierry Gil
,
Nadine Azemard
,
Jérôme Thireau
,
Alain Lacampagne
et al.
Communication dans un congrès
hal-02903236
v1
|
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NeurONN: Neuromorphic Computing for Artificial Intelligence at the Edge
Stefania Carapezzi
,
Madeleine Abernot
,
Corentin Delacour
,
Nadine Azemard
,
Jérémie Salles
et al.
3rd AI Compute Symposium (IBM IEEE CAS/EDS), Oct 2020, Zurich (virtual), Switzerland
Communication dans un congrès
lirmm-03009213
v1
|
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EU H2020 NEURONN: Two-Dimensional Oscillatory Neural Networks for Energy Efficient Neuromorphic Computing
Aida Todri-Sanial
,
Stefania Carapezzi
,
Corentin Delacour
,
Madeleine Abernot
,
Eirini Karachristou
et al.
EFECS 2020 - European Forum for Electronic Components and Systems, Nov 2020, Brussels, Belgium
Communication dans un congrès
lirmm-03024126
v1
|
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Combined analysis of supply voltage and body-bias voltage for energy management
Rida Kheirallah
,
Jean-Marc J.-M. Galliere
,
Nadine Azemard
,
Gilles R. Ducharme
Communication dans un congrès
lirmm-01867809
v1
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Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic
Nicolas Jeanniot
,
Gaël Pillonnet
,
Pascal Nouet
,
Nadine Azemard
,
Aida Todri-Sanial
Communication dans un congrès
lirmm-01768831
v1
|
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Atomistic to circuit level modeling of defective doped SWCNTs with contacts for on-chip interconnect application
Jie Liang
,
Lee Jaehyun
,
Salim Berrada
,
Vihar P. Georgiev
,
Asenov Asen
et al.
Communication dans un congrès
lirmm-01880220
v1
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Physical description and analysis of doped carbon nanotube interconnects
Jie Liang
,
Liuyang Zhang
,
Nadine Azemard
,
Pascal Nouet
,
Aida Todri-Sanial
Communication dans un congrès
lirmm-01457338
v1
|
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Statistical Energy Study for 28nm FDSOI Technology
Rida Kheirallah
,
Gilles R. Ducharme
,
Nadine Azemard
VARI: Workshop on CMOS Variability, Sep 2015, Salvador, Bahia, Brazil
Communication dans un congrès
lirmm-01256280
v1
|
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Statistical Energy Study for 28nm FDSOI Devices
Rida Kheirallah
,
Jean-Marc J.-M. Galliere
,
Aida Todri-Sanial
,
Gilles R. Ducharme
,
Nadine Azemard
EuroSimE: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, Apr 2015, Budapest, Hungary. ⟨10.1109/EuroSimE.2015.7103149⟩
Communication dans un congrès
lirmm-01168602
v1
|
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VARI Worshop Overview
Nadine Azemard
DCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.159-161
Communication dans un congrès
lirmm-00762113
v1
|
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Statistical Cells Timing Metrics Characterization
Nadine Azemard
,
Zeqin Wu
,
Philippe Maurine
,
Gilles R. Ducharme
FTFC: Faible Tension - Faible Consommation, Jun 2012, Paris, France
Communication dans un congrès
lirmm-00762131
v1
|
|
Characterizing Statistical Cells Timing Metrics with Semi-Monte-Carlo Method
Nadine Azemard
,
Zeqin Wu
,
Philippe Maurine
,
Gilles R. Ducharme
VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2011, Hong-Kong, China
Communication dans un congrès
lirmm-00617606
v1
|
|
Statistical Timing Characterization of Standard Cells with Semi-Monte-Carlo Method
Nadine Azemard
,
Zeqin Wu
,
Philippe Maurine
,
Gilles R. Ducharme
VARI: Workshop on CMOS Variaility, May 2011, Grenoble, France
Communication dans un congrès
lirmm-00617593
v1
|
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SSTA with Delay Correlations
Zeqin Wu
,
Philippe Maurine
,
Nadine Azemard
,
Gilles R. Ducharme
Communication dans un congrès
lirmm-00504882
v1
|
|
SSTA with Cell-to-Cell Delay Correlations
Zeqin Wu
,
Philippe Maurine
,
Nadine Azemard
,
Gilles R. Ducharme
VARI: Workshop on CMOS Variability, May 2010, Montpellier, France
Communication dans un congrès
lirmm-00546322
v1
|
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On-Chip Process Variability Monitoring
Nabila Moubdi
,
Philippe Maurine
,
Robin M. Wilson
,
Nadine Azemard
,
Vincent Dumettier
et al.
VARI: Workshop on CMOS Variability, May 2010, Montpellier, France
Communication dans un congrès
lirmm-00546337
v1
|
|
Voltage Scaling and Body Biasing Methodology for High Performance Hardwired LDPC
Nabila Moubdi
,
Philippe Maurine
,
Nadine Azemard
,
Robin M. Wilson
,
Sylvain Engels
Communication dans un congrès
lirmm-00546316
v1
|
|
Computing Delay Correlations in SSTA
Zeqin Wu
,
Philippe Maurine
,
Nadine Azemard
,
Gilles R. Ducharme
ICICDT: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.130-133, ⟨10.1109/ICICDT.2010.5510277⟩
Communication dans un congrès
lirmm-00546301
v1
|
|
On-Chip Timing Slack Monitoring
Bettina Rebaud
,
Marc Belleville
,
Edith Beigné
,
Michel Robert
,
Philippe Maurine
et al.
Communication dans un congrès
lirmm-00429350
v1
|
|
Interpretation of SSTA Results
Zeqin Wu
,
Nadine Azemard
,
Philippe Maurine
,
Gilles R. Ducharme
FTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Switzerland
Communication dans un congrès
lirmm-00374060
v1
|
|
Product On-Chip Process Compensation for Low Power and Yield Enhancement
Nabila Moubdi
,
Philippe Maurine
,
Robin M. Wilson
,
Nadine Azemard
,
Vincent Dumettier
et al.
Communication dans un congrès
istex
lirmm-00433504
v1
|
|
Digital Timing Slack Monitors and their Specific Insertion Flow for Adaptive Compensation of Variabilities
Bettina Rebaud
,
Marc Belleville
,
Edith Beigné
,
Christian Bernard
,
Michel Robert
et al.
Communication dans un congrès
istex
lirmm-00433462
v1
|
|
Un nouveau système d'instrumentation en ligne pour la caractérisation et l'adaptation dynamique aux variations
Bettina Rebaud
,
Marc Belleville
,
Edith Beigné
,
Michel Robert
,
Philippe Maurine
et al.
FTFC: Faible Tension - Faible Consommation, Jun 2009, Neuchâtel, Suisse
Communication dans un congrès
lirmm-00404810
v1
|
|
An Innovative Timing Slack Monitor for Variation Tolerant Circuits
Bettina Rebaud
,
Marc Belleville
,
Edith Beigné
,
Michel Robert
,
Philippe Maurine
et al.
Communication dans un congrès
lirmm-00371174
v1
|
|
On-Chip Process Variability Monitoring
Nabila Moubdi
,
Robin M. Wilson
,
Sylvain Engels
,
Nadine Azemard
,
Philippe Maurine
DATE: Design, Automation and Test in Europe, Apr 2009, Nice, France
Communication dans un congrès
lirmm-00374368
v1
|
|
Interpreting SSTA Results with Correlation
Zeqin Wu
,
Philippe Maurine
,
Nadine Azemard
,
Gilles R. Ducharme
Communication dans un congrès
istex
lirmm-00433505
v1
|
|
SSTA Considering Switching Process Induced Correlations
Zeqin Wu
,
Philippe Maurine
,
Nadine Azemard
,
Gilles R. Ducharme
Communication dans un congrès
lirmm-00340564
v1
|
|
Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier
Bettina Rebaud
,
Marc Belleville
,
Christian Bernard
,
Zeqin Wu
,
Michel Robert
et al.
ISVLSI: International Symposium on Very Large Scale Integration, Apr 2008, Montpellier, France. pp.316-321, ⟨10.1109/ISVLSI.2008.70⟩
Communication dans un congrès
lirmm-00280809
v1
|
|
SSTA with Structure Correlations Considering input Slope and Output Load Variations
Zeqin Wu
,
Philippe Maurine
,
Nadine Azemard
,
Gilles R. Ducharme
GDR SOC-SIP, Jun 2008, Paris, France. pp.3
Communication dans un congrès
lirmm-00340231
v1
|
|
SSTA with Correlations Considering input Slope and Output Load Variations
Zeqin Wu
,
Philippe Maurine
,
Nadine Azemard
,
Gilles R. Ducharme
VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2008, Rhodes Island, Greece. pp.164-167
Communication dans un congrès
lirmm-00332757
v1
|
|
Étude des violations de temps d'établissement et de maintien dues aux variations du processus de fabrication dans un opérateur arithmétique
Bettina Rebaud
,
Zeqin Wu
,
Marc Belleville
,
Christian Bernard
,
Michel Robert
et al.
JNRDM 2008 - 11e Journées Nationales du Réseau Doctoral de Microélectronique, May 2008, Bordeaux, France
Communication dans un congrès
lirmm-00281175
v2
|
|
A Comparative Study of Variability Impact on Static Flip-Flop Timing Characteristics
Bettina Rebaud
,
Marc Belleville
,
Christian Bernard
,
Michel Robert
,
Patrick Maurine
et al.
ICICDT: International Conference on IC Design and Technology, Jun 2008, Grenoble, France. pp.167-170
Communication dans un congrès
lirmm-00305246
v1
|
|
Impact de la variabilité des caractéristiques temporelles des cellules combinatoires et séquentielles sur un opérateur numérique
Bettina Rebaud
,
Marc Belleville
,
Christian Bernard
,
Zeqin Wu
,
Michel Robert
et al.
FTFC: Faible Tension - Faible Consommation, May 2008, Louvain-La-Neuve, Belgique
Communication dans un congrès
lirmm-00283731
v1
|
|
SSTA Considering Effects of Structure Correlations, Input Slope and Output Load Variations
Zeqin Wu
,
Philippe Maurine
,
Gilles R. Ducharme
,
Nadine Azemard
FTFC: Faible Tension - Faible Consommation, May 2008, Louvain-la-Neuve, Belgium. pp.39-43
Communication dans un congrès
lirmm-00288537
v1
|
|
Conditional Moments based SSTA Considering Switching Process Induced Correlations
Zeqin Wu
,
Philippe Maurine
,
Gilles R. Ducharme
,
Nadine Azemard
DCIS: Design of Circuits and Integrated Systems, Nov 2008, Grenoble, France. pp.70-77
Communication dans un congrès
lirmm-00340221
v1
|
|
A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation
Vincent Migairou
,
Robin Wilson
,
Sylvain Engels
,
Zeqin Wu
,
Nadine Azemard
et al.
FTFC: Faible Tension - Faible Consommation, May 2007, Paris, France. pp.19-25
Communication dans un congrès
lirmm-00178454
v1
|
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Une Famille d'Additionneurs Asynchrones CMOS Bundled Data à Temps de Calcul Dépendant aux Données
Robin Perrot
,
Nadine Azemard
,
Philippe Maurine
FTFC: Faible Tension - Faible Consommation, May 2007, Paris, France. pp.75-80
Communication dans un congrès
lirmm-00178466
v1
|
|
A Simple Statistical Timing Analysis Flow and its Application to Timing Margin Evaluation
Vincent Migairou
,
Robin Wilson
,
Sylvain Engels
,
Zeqin Wu
,
Nadine Azemard
et al.
Communication dans un congrès
istex
lirmm-00175076
v1
|
|
Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops
Benoit Lasbouygues
,
Robin M. Wilson
,
Nadine Azemard
,
Philippe Maurine
Communication dans un congrès
lirmm-00178525
v1
|
|
Une Famille d'Additionneur Asynchrones CMOS à Temps de Calcul Dépendant de Données
Robin Perrot
,
Nadine Azemard
,
Philippe Maurine
JNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France. pp.469-472
Communication dans un congrès
lirmm-00102842
v1
|
|
Statistical Characterization of Library Timing Performance
Vincent Migairou
,
Robin P. Wilson
,
Sylvain Engels
,
Nadine Azemard
,
Philippe Maurine
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2006, Montpellier, France. pp.468-476, ⟨10.1007/11847083_45⟩
Communication dans un congrès
istex
lirmm-00093233
v1
|
|
Request-Skip Adders: CMOS Standard Cell Data Dependent Adders
Robin Perrot
,
Nadine Azemard
,
Philippe Maurine
Communication dans un congrès
lirmm-00130195
v1
|
|
Circuit Performance Optimization under Delay Constraints
Alexandre Verle
,
Alexis Landrault
,
Philippe Maurine
,
Nadine Azemard
DCIS: Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain
Communication dans un congrès
lirmm-00117119
v1
|
|
Timing Analysis in Presence of Voltage Drops and Temperature Gradients
Benoit Lasbouygues
,
Robin M. Wilson
,
Nadine Azemard
,
Philippe Maurine
TAU: Timing Issues in the Specification and Synthesis of Digital Systems, Feb 2006, San Jose, CA, United States. pp.28-34
Communication dans un congrès
lirmm-00106705
v1
|
|
Exploration of the Area-Latency Tradeoff of Asynchronous CMOS data Dependent Adders
Robin Perrot
,
Philippe Maurine
,
Nadine Azemard
DCIS: Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain
Communication dans un congrès
lirmm-00117102
v1
|
|
Timing Analysis in Presence of Supply Voltage and Temperature Variations
Benoit Lasbouygues
,
Robin M. Wilson
,
Nadine Azemard
,
Philippe Maurine
Communication dans un congrès
lirmm-00102760
v1
|
|
Circuit Sizing Method under Delay Constraint
Alexandre Verle
,
Alexis Landrault
,
Philippe Maurine
,
Nadine Azemard
Communication dans un congrès
lirmm-00106911
v1
|
|
Synthèse Physique et Optimisation des Performances au Niveau Transistor
Alexis Landrault
,
Alexandre Verle
,
Philippe Maurine
,
Nadine Azemard
FTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.91-95
Communication dans un congrès
lirmm-00106004
v1
|
|
Optimization Protocol Based on Low Power Metrics
Alexandre Verle
,
Alexis Landrault
,
Philippe Maurine
,
Nadine Azemard
IWLS: International Workshop on Logic Synthesis, Jun 2005, Lake Arrowhead Resort, CA, United States. pp.288-293
Communication dans un congrès
lirmm-00106018
v1
|
|
Path Optimization Protocol Based on Speed Low Power Metrics
Alexandre Verle
,
Alexis Landrault
,
Philippe Maurine
,
Nadine Azemard
Communication dans un congrès
lirmm-00106428
v1
|
|
Temperature Dependency in UDSM Process
Benoit Lasbouygues
,
Robin M. Wilson
,
Philippe Maurine
,
Nadine Azemard
,
Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.693-703, ⟨10.1007/11556930_71⟩
Communication dans un congrès
istex
lirmm-00106077
v1
|
|
Circuit Optimization Based on Speed Indicators
Alexandre Verle
,
Alexis Landrault
,
Philippe Maurine
,
Nadine Azemard
Communication dans un congrès
lirmm-00106439
v1
|
|
Low Power Oriented CMOS Circuit Optimization Protocol
Alexandre Verle
,
Xavier Michel
,
Nadine Azemard
,
Philippe Maurine
,
Daniel Auvergne
DATE 2005 - 8th Design, Automation and Test in Europe Conference and Exhibition, Mar 2005, Munich, Germany. pp.640-645, ⟨10.1109/DATE.2005.202⟩
Communication dans un congrès
lirmm-00106452
v1
|
|
Additionneurs RCA Data Dependent Micropipelines
Robin Perrot
,
Nadine Azemard
,
Philippe Maurine
FTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.183-188
Communication dans un congrès
lirmm-00106005
v1
|
|
Speed Indicators for Circuit Optimization
Alexandre Verle
,
Alexis Landrault
,
Philippe Maurine
,
Nadine Azemard
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.618-628, ⟨10.1007/11556930_63⟩
Communication dans un congrès
istex
lirmm-00106076
v1
|
|
Protocole d'Optimisation de Circuit CMOS Orienté Basse Puissance
Alexandre Verle
,
Xavier Michel
,
Philippe Maurine
,
Nadine Azemard
FTFC: Faible Tension - Faible Consommation, May 2005, Paris, France. pp.17-22
Communication dans un congrès
lirmm-00106002
v1
|
|
Ripple Carry Adder for Micropipeline Circuits
Robin Perrot
,
Nadine Azemard
,
Philippe Maurine
DCIS 2005 - 20th Conference on Design of Circuits and Integrated Systems, Nov 2005, Lisbonne, Portugal
Communication dans un congrès
lirmm-00106075
v1
|
|
Automatic Layout Synthesis Based Performance Optimization
Alexis Landrault
,
Nadine Azemard
,
Philippe Maurine
,
Michel Robert
,
Daniel Auvergne
IWLS: International Workshop on Logic Synthesis, Jun 2004, Temecula, CA, United States. pp.80-85
Communication dans un congrès
lirmm-00108654
v1
|
|
Delay Bound Based CMOS Gate Sizing Technique
Alexandre Verle
,
Xavier Michel
,
Philippe Maurine
,
Nadine Azemard
,
Daniel Auvergne
Communication dans un congrès
lirmm-00108856
v1
|
|
Optimization Protocol Based on Performance Metric
Xavier Michel
,
Alexandre Verle
,
Nadine Azemard
,
Philippe Maurine
,
Daniel Auvergne
DCIS 2004 - 19th International Conference on Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.964-968
Communication dans un congrès
lirmm-00108935
v1
|
|
Design Optimization with Automated Cell Generation
Alexis Landrault
,
Nadine Azemard
,
Philippe Maurine
,
Michel Robert
,
Daniel Auvergne
Communication dans un congrès
istex
lirmm-00108894
v1
|
|
RC on-chip interconnect Performance revisited
Philippe Maurine
,
Nadine Azemard
,
Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.809-814
Communication dans un congrès
lirmm-00108934
v1
|
|
Definition of P/N Width Ratio for CMOS Standard Cell Library
Alexandre Verle
,
Philippe Maurine
,
Nadine Azemard
,
Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.769-773
Communication dans un congrès
lirmm-00108933
v1
|
|
Physical Extension of the Logical Effort Model
Benoit Lasbouygues
,
Robin M. Wilson
,
Philippe Maurine
,
Nadine Azemard
,
Daniel Auvergne
Communication dans un congrès
istex
lirmm-00108895
v1
|
|
Temperature Dependence in Low Power CMOS UDSM Process
Benoit Lasbouygues
,
Robin M. Wilson
,
Philippe Maurine
,
Nadine Azemard
,
Daniel Auvergne
Communication dans un congrès
istex
lirmm-00108893
v1
|
|
Performance Metric Based Optimization Protocol
Xavier Michel
,
Alexandre Verle
,
Philippe Maurine
,
Nadine Azemard
,
Daniel Auvergne
Communication dans un congrès
istex
lirmm-00108892
v1
|
|
Définition d'une Métrique d'Insertion de Buffers
Xavier Michel
,
Alexandre Verle
,
Nadine Azemard
,
Philippe Maurine
,
Daniel Auvergne
FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.131-136
Communication dans un congrès
lirmm-00269520
v1
|
|
Représentation Unifiée des Performances Temporelles d'une Bibliothèque de Cellules Standards
Benoit Lasbouygues
,
J. Schindler
,
Sylvain Engels
,
Philippe Maurine
,
Nadine Azemard
et al.
FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.119-124
Communication dans un congrès
lirmm-00269519
v1
|
|
CMOS Gate Sizing under Delay Constraint
Alexandre Verle
,
Xavier Michel
,
Philippe Maurine
,
Nadine Azemard
,
Daniel Auvergne
Communication dans un congrès
istex
lirmm-00244021
v1
|
|
Dimensionnement de Portes CMOS Sous Contrainte de Délai
Alexandre Verle
,
Xavier Michel
,
Philippe Maurine
,
Nadine Azemard
,
Daniel Auvergne
FTFC: Faible Tension - Faible Consommation, May 2003, Paris, France. pp.111-117
Communication dans un congrès
lirmm-00269522
v1
|
|
Continuous Representation of the Performance of a CMOS Library
Benoit Lasbouygues
,
J. Schindler
,
Sylvain Engels
,
Philippe Maurine
,
Xavier Michel
et al.
Communication dans un congrès
lirmm-00239459
v1
|
|
Metric Definition for Circuit Speed Optimization
Xavier Michel
,
Alexandre Verle
,
Nadine Azemard
,
Philippe Maurine
,
Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2003, Turin, Italy. pp.451-460
Communication dans un congrès
lirmm-00269568
v1
|
|
Timing Performance Representation of a CMOS Standard Cell Library
Benoit Lasbouygues
,
J. Schindler
,
Sylvain Engels
,
Philippe Maurine
,
Xavier Michel
et al.
DCIS: Design of Circuits and Integrated Systems, Nov 2003, Ciudad Real, Spain. pp.83-88
Communication dans un congrès
lirmm-00239460
v1
|
|
Metric Definition for Circuit Speed Optimization
Xavier Michel
,
Alexandre Verle
,
Philippe Maurine
,
Nadine Azemard
,
Daniel Auvergne
IWLS: International Workshop on Logic Synthesis, May 2003, Laguna Beach, CA, United States
Communication dans un congrès
lirmm-00269689
v1
|
|
Structure Independent Representation of Output Transition Time for CMOS Library
Philippe Maurine
,
Nadine Azemard
,
Daniel Auvergne
Communication dans un congrès
istex
lirmm-00244012
v1
|
|
Defining the Maximum Speed of CMOS Gate Library
Philippe Maurine
,
Nadine Azemard
,
Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 2002, Santander, Spain. pp.81-86
Communication dans un congrès
lirmm-00239455
v1
|
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Gate Speed Improvement at Minimal Power Dissipation
Philippe Maurine
,
Xavier Michel
,
Nadine Azemard
,
Daniel Auvergne
APPCAS: Asia-Pacific Conference on Circuits and Systems, Oct 2002, Denpasar, Bali, pp.278-282
Communication dans un congrès
lirmm-00239453
v1
|
|
Metric Definition for Buffer Insertion
Xavier Michel
,
Philippe Maurine
,
Nadine Azemard
,
Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 2002, Santander, Spain. pp.307-312
Communication dans un congrès
lirmm-00239458
v1
|
|
Evaluation et Optimisation de Chemins Combinatoires
Xavier Michel
,
Philippe Maurine
,
Nadine Azemard
,
Daniel Auvergne
Colloque du GDR CAO de Circuits et Systèmes Intégrés, May 2002, Paris, France. pp.173-176
Communication dans un congrès
lirmm-00269329
v1
|
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Delay Bound Determination for Timing Closure Satisfaction
Nadine Azemard
,
Michel Aline
,
Daniel Auvergne
Communication dans un congrès
lirmm-00241322
v1
|
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Deep Submicron Switching Current Modeling for CMOS Logic Output Transition Time Determination
Philippe Maurine
,
Nadine Azemard
,
Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2001, Yverdon-Les-Bains, Switzerland. pp.5.3.1-5.3.10
Communication dans un congrès
lirmm-00244010
v1
|
|
Delay Bound Determination for Timing Closure on CMOS Circuits
Nadine Azemard
,
Michel Aline
,
Philippe Maurine
,
Daniel Auvergne
IWLS: International Workshop on Logic and Synthesis, Jun 2001, Granlibakken Conference Center, United States. pp.96-100
Communication dans un congrès
lirmm-00244007
v1
|
|
Full Analyttical Model for delay Performance Estimation in Submicron CMOS
Philippe Maurine
,
Nadine Azemard
,
Daniel Auvergne
MIXDES: Mixed Design of Integrated Circuits and Systems, Jun 2001, Zakopane, Poland. pp.355-359
Communication dans un congrès
lirmm-00239444
v1
|
|
Performance Indicators for Designing CMOS Logic
Philippe Maurine
,
Nadine Azemard
,
Daniel Auvergne
Communication dans un congrès
lirmm-00239446
v1
|
|
Technological Assignment for a Minimal Power Consumption
Philippe Maurine
,
Nadine Azemard
,
Daniel Auvergne
VLSI-SoC: Very Large Scale Integration - System-on-Chip, Dec 2001, Montpellier, France. pp.236-241
Communication dans un congrès
lirmm-00239450
v1
|
|
Timing Closure Management based on Delay Bound Determination
Nadine Azemard
,
Michel Aline
,
Philippe Maurine
,
Daniel Auvergne
VLSI-SoC: Very Large Scale Integration - System-on-Chip, Dec 2001, Montpellier, France. pp.430-434
Communication dans un congrès
lirmm-00239452
v1
|
|
Switching Current Modeling in CMOS Inverter for Speed and Power Estimation
Philippe Maurine
,
Régis Poirier
,
Nadine Azemard
,
Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 2001, Porto, Portugal. pp.618-622
Communication dans un congrès
lirmm-00239448
v1
|
|
A Physical Synthesis Design Flow based on Virtual Components
Fernando Gehm Moraes
,
Michel Robert
,
Daniel Auvergne
,
Nadine Azemard
DCIS: Design of Circuits and Integrated Systems, Nov 2000, Montpellier, France. pp.740-745
Communication dans un congrès
lirmm-00239439
v1
|
|
Upper and Lower bound Determination of delay on Critical Path
Michel Aline
,
Nadine Azemard
,
Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 2000, Montpellier, France. pp.543-547
Communication dans un congrès
lirmm-00239437
v1
|
|
Delay Bound Determination for Path Constraint Satisfaction
Nadine Azemard
,
Michel Aline
,
Daniel Auvergne
ISMA: International Symposium on Microelectronics and Assembly, Nov 2000, Singapour, China. pp.122-129, ⟨10.1117/12.405403⟩
Communication dans un congrès
lirmm-00241266
v1
|
|
POPS: A tool for Delay/Power Performance/Optimization
Nadine Azemard
,
Michel Aline
,
Daniel Auvergne
Communication dans un congrès
lirmm-00239434
v1
|
|
Post Layout Management of Delay Power Constraints in Submicronic CMOS Implementation
Nadine Azemard
,
Michel Aline
,
Daniel Auvergne
IWLS: International Workshop on Logic Synthesis, Jun 1999, Lake Tahoe, CA, United States. pp.198-201
Communication dans un congrès
lirmm-00244002
v1
|
|
Delay-Power Performance Analysis
Séverine Cremoux
,
Michel Aline
,
Nadine Azemard
,
Daniel Auvergne
ICECS: International Conference on Electronics, Circuits and Systems, Sep 1999, Pafos, Cyprus. pp.1543-1546, ⟨10.1109/ICECS.1999.814465⟩
Communication dans un congrès
lirmm-00239424
v1
|
|
Local Gate Resizing for Critical Path Optimization
Nadine Azemard
,
Michel Aline
,
Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 1999, Palma de Majorque, Spain. pp.195-200
Communication dans un congrès
lirmm-00239429
v1
|
|
Satisfaction of Delay/Power Constraints by Iterative Gate Sizing
Nadine Azemard
,
Michel Aline
,
Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1999, Kos, Greece. pp.325-334
Communication dans un congrès
lirmm-00244003
v1
|
|
A New Tool for Path Performance Optimization
Séverine Cremoux
,
Nadine Azemard
,
Michel Aline
,
Daniel Auvergne
International Workshop on IP Based Synthesis and System Design, Dec 1998, Grenoble, France. pp.175-179
Communication dans un congrès
lirmm-00241408
v1
|
|
Path Selection for Delay and Power Performance Optimization
Séverine Cremoux
,
Nadine Azemard
,
Daniel Auvergne
SAME: Sophia Antipolis Forum on Microelectronics, Oct 1998, Sophia Antipolis, France. pp.48-53
Communication dans un congrès
lirmm-00239415
v1
|
|
POPS: Performance Optimization by Path Selection
Séverine Cremoux
,
Nadine Azemard
,
Michel Aline
,
Daniel Auvergne
DCIS: Design of Circuits and Integrated Systems, Nov 1998, Madrid, Spain. pp.10-15
Communication dans un congrès
lirmm-00239421
v1
|
|
Path Resizing Based on Incremental Technique
Séverine Cremoux
,
Nadine Azemard
,
Daniel Auvergne
Communication dans un congrès
lirmm-00241190
v1
|
|
Long and Short Path Sizing for Delay-Power Performance Management
Séverine Cremoux
,
Nadine Azemard
,
Daniel Auvergne
IWLS: International Workshop on Logic Synthesis, Jun 1998, Lake Tahoe, CA, United States
Communication dans un congrès
lirmm-00241376
v1
|
|
POPS: A New Tool for Path Evaluation
Séverine Cremoux
,
Nadine Azemard
,
Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1998, Lyngby, Denmark. pp.235-244
Communication dans un congrès
lirmm-00241378
v1
|
|
Selective Gate Sizing for Delay/Power Performance Management
Séverine Cremoux
,
Nadine Azemard
,
Daniel Auvergne
IWLAS: International Workshop on Logic and Architecture Synthesis, Dec 1997, Grenoble, France
Communication dans un congrès
lirmm-00241374
v1
|
|
A Path Sensitization Approach for Performance Optimization
Thierry Monnier
,
Séverine Cremoux
,
Nadine Azemard
,
Daniel Auvergne
ISIC: International Symposium on IC Technology, Systems and Applications, Sep 1997, Singapore, China. pp.94-97
Communication dans un congrès
lirmm-00241160
v1
|
|
Performance Otimization by Path Selection
Séverine Cremoux
,
Thierry Monnier
,
Nadine Azemard
,
Daniel Auvergne
IWLS: International Workshop on Logic Synthesis, May 1997, Tahoe City, CA, United States. pp.152-155
Communication dans un congrès
lirmm-00241372
v1
|
|
Path Sensitization for Performance Optimization
Séverine Cremoux
,
Jose Luis Guntzel
,
Nadine Azemard
,
Daniel Auvergne
MIXDES: Mixed Design of Integrated Circuits and Systems, Jun 1997, Poznan, Poland. pp.195-200
Communication dans un congrès
lirmm-00239409
v1
|
|
A Path Selection Algorithm for Performance Optimization
Séverine Cremoux
,
Thierry Monnier
,
Jose Luis Guntzel
,
Nadine Azemard
,
Daniel Auvergne
IWLAS: International Workshop on Logic and Architecture Synthesis, Dec 1996, Grenoble, France. pp.277-284
Communication dans un congrès
lirmm-00241369
v1
|
|
Design and Selection of Buffers for Minimum Power-Delay Product
Sandra Turgis
,
Nadine Azemard
,
Daniel Auvergne
Communication dans un congrès
lirmm-00239400
v1
|
|
Short-Circuit Power Dissipation calculation on CMOS Inverters using the Equivalent Short-Circuit Capacitance Concept
Sandra Turgis
,
Nadine Azemard
,
Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1995, Oldenburg, Germany. pp.213-224
Communication dans un congrès
lirmm-00241367
v1
|
|
Explicit Evaluation of Short Circuit Power Dissipation for CMOS Logic Structures
Sandra Turgis
,
Nadine Azemard
,
Daniel Auvergne
ISLPD: International Symposium on Low Power Design, Apr 1995, Dana Point, CA, United States. pp.129-134, ⟨10.1145/224081.224104⟩
Communication dans un congrès
lirmm-00241153
v1
|
|
Design and Sizing of Tapered Buffers for Minimum Power-Delay Product
Sandra Turgis
,
Nadine Azemard
,
Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1995, Oldenburg, Germany. pp.79-90
Communication dans un congrès
lirmm-00241366
v1
|
|
Standard Cell Performance Modelling
Myrian Mellah
,
Nadine Azemard
,
Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1994, Barcelone, Spain. pp.158-167
Communication dans un congrès
lirmm-00241364
v1
|
|
General Determination of Buffer Insertion Limits
Myrian Mellah
,
Nadine Azemard
,
Daniel Auvergne
IWoDA: International Workshop on Design Automation, Jun 1994, Moscou, Russia. pp.21-23
Communication dans un congrès
lirmm-00241361
v1
|
|
A Real Characterization based Buffer Selection Algorithm
Nadine Azemard
,
Sylvie Amat
,
Myrian Mellah
,
Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Oct 1993, La Grande Motte, France
Communication dans un congrès
lirmm-00241350
v1
|
|
Tool Box for Performance Driven Macrocell layout Synthesis
Fernando Gehm Moraes
,
Nadine Azemard
,
Michel Robert
,
Daniel Auvergne
Eurochip Workshop on VLSI Design Training, Sep 1993, Toledo, Spain. pp.56-61
Communication dans un congrès
lirmm-00241348
v1
|
|
Evaluation of Speed up Strategy from Gate Performance Modelling
Daniel Auvergne
,
Sylvie Amat
,
Myrian Mellah
,
Nadine Azemard
,
Michel Robert
IFIP Workshop on Logic and Architecture Synthesis, Dec 1993, Grenoble, France, pp.193-208
Communication dans un congrès
lirmm-00241358
v1
|
|
Flexible Macrocell layout Generator
Fernando Gehm Moraes
,
Nadine Azemard
,
Michel Robert
,
Daniel Auvergne
4th ACM/SIGDA Physical Design Workshop, Layout Synthesis for the New Generation of VLSI ASIC Technologies, Apr 1993, UCLA Conference Center, CA, USA, pp.105-116
Communication dans un congrès
lirmm-00241344
v1
|
|
Application of Explicit Delay Time Modelling to CMOS Data Path Evaluation and Transistor Sising
Nadine Azemard
,
Denis Deschacht
,
Michel Robert
,
Daniel Auvergne
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 1992, Paris, France. pp.102-108
Communication dans un congrès
lirmm-00241327
v1
|
|
P.SIZE: A Sizing aid for Optimized Designs
Nadine Azemard
,
Vincent Bonzom
,
Daniel Auvergne
Communication dans un congrès
lirmm-00239396
v1
|
|
Optimization Technique for Performance driven Cell Generator
Nadine Azemard
,
Vincent Bonzom
,
Sylvie Amat
,
Daniel Auvergne
EuroASIC 1992 - European Conference on Application Specific Integrated Circuits, Jun 1992, Paris, France. pp.152-155, ⟨10.1109/EUASIC.1992.228032⟩
Communication dans un congrès
lirmm-00239390
v1
|
|
An Accurate and Efficient Delay Time Modelling and its Application to CMOS Data Path Evaluation and Transistor Sizing
Daniel Auvergne
,
Nadine Azemard
,
Denis Deschacht
,
Michel Robert
World Congress on Computation and Applied Mathematics, IMACS: International Association for Mathematics and Computers in Simulation, Jul 1991, Dublin, Ireland. pp.1661-1663
Communication dans un congrès
lirmm-00239387
v1
|
|
Formal Sizing Rules of CMOS Circuits
Daniel Auvergne
,
Nadine Azemard
,
Vincent Bonzom
,
Denis Deschacht
,
Michel Robert
Communication dans un congrès
lirmm-00239374
v1
|
|
Evaluation of VLSI Layout Implementation for Efficiency
Michel Robert
,
Joel Trauchessec
,
Guy Cathébras
,
Vincent Bonzom
,
Nadine Azemard
et al.
EURO-ASIC 1991 - European Conference on Design Automation with European Event in ASIC Design, May 1991, Paris, France. pp.362-365, ⟨10.1109/EUASIC.1991.212836⟩
Communication dans un congrès
lirmm-00239384
v1
|
|
CMOS Circuit Speed Optimization based on Closed form Equation
Nadine Azemard
,
Vincent Bonzom
International Students Microelectronic Conference, May 1990, Zagreb, Yugoslavia, pp.29-32
Communication dans un congrès
lirmm-00239369
v1
|