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Pierre Boulet
137
Documents
Researcher identifiers
pboulet
- ResearcherId : K-7600-2015
- IdRef : 069782644
-
0000-0002-0373-4478
- Google Scholar : https://scholar.google.fr/citations?hl=fr&user=gzy0ay0AAAAJ
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Multi-objective Mapping for NoC Architectures1st International Conference on Digital Communications and Computer Applications, 2007, Irbid, Jordan. pp.132-139
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MDA for SoC Embedded Design, Intensive Signal Processing ExperimentSIVOES-MDA, 2003, San Francisco, United States
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Sophocles: Cyber-Enterprise for System-on-Chip Distributed Simulation -- Model UnificationIFIP International Workshop on IP Based System-on-Chip Design, 2003, Grenoble, France
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Conference papers
inria-00565188v1
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Parallelization of a Fortran 90 Program for Electromagnetic Problems3rd Annual HPF User Group Meeting, HUG'99, 1999, Redondo Beach, CA, United States
Conference papers
inria-00565189v1
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Communication Pre-evaluation in HPFEuro-Par'98, 1998, Southampton, United Kingdom. pp.263-272
Conference papers
inria-00565190v1
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Scanning polyhedra without DO-loopsPACT'98, 1998, Paris, France. pp.4-11
Conference papers
inria-00564990v1
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Code generation in BouclettesProceedings of the Fifth Euromicro Workshop on Parallel and Distributed Processing, 1997, London, United Kingdom. pp.273--280
Conference papers
inria-00565001v1
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Evaluation of Automatic Parallelization Strategies for HPF CompilersHPCN 96, 1996, Bruxelles, Belgium. pp.778-783
Conference papers
inria-00564994v1
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Bouclettes: A Fortran Loop ParallelizerHPCN 96, 1996, Bruxelles, Belgium. pp.784-791
Conference papers
inria-00564993v1
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Heuristics for the evaluation of array expressions on state-of-the-art massively parallel machinesAlgorithms and Parallel VLSI Architectures III, 1995, Unknown, pp.319-330
Conference papers
hal-00857100v1
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Experimental Evaluation of Affine Schedules for Matrix Multiplication on the MasPar ArchitectureProceedings MPCS'94, 1994, Ischia, Italy. pp.452--459
Conference papers
inria-00565005v1
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(Pen)-ultimate tiling?Proceedings of the IEEE Scalable High Performance Computing Conference, 1994, Knoxville, TN, United States. pp.568-576
Conference papers
inria-00564995v1
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Evaluating array expressions on massively parallel machines with communication/computation overlapParallel Processing: CONPAR94 - VAPP VI, 1994, Unknown, pp.713-724
Conference papers
hal-00857085v1
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Spiking Neural Computing in Memristive Neuromorphic PlatformsSpringer Nature, Handbook of Memristor Networks, , inPress, 978-3-319-76375-0. ⟨10.1007/978-3-319-76375-0_25⟩
Book sections
hal-02172472v1
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Static and Dynamic Mapping Heuristics for Multiprocessor Systems-on-ChipGamatié, Abdoulaye. Computing in Research and Development in Africa, Springer International Publishing, pp.229--247, 2014, 978-3-319-08238-7 978-3-319-08239-4
Book sections
hal-01198993v1
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Design Space Exploration for Efficient Data Intensive Computing on SoCsBorko Furht and Armando Escalante. Handbook of Data Intensive Computing, Springer, 2011
Book sections
inria-00637012v1
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UML2 Profile for Modeling Controlled Data Parallel ApplicationsHuss, Sorin Alexander. Advances in Design and Specification Languages for SoCs, Selected contributions from FDL'06, Springer, 2007, ChDL
Book sections
inria-00565161v1
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Towards Distributed Process Networks with CORBAFrédéric Desprez. Algorithms and Tools for Parallel Computing On Heterogeneous Clusters, Nova Science Publishers, Inc, 2006
Book sections
inria-00565166v1
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Model Driven Engineering for System-on-Chip DesignJean-Philippe Babau and Joël Champeau and Sébastien Gérard. From MDD concepts to experiments and illustrations, ISTE, Hermes science and Lavoisier, 2006, 1-905209-59-0
Book sections
inria-00565165v1
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Model Driven Architecture for Intensive Embedded SystemsSébastien Gérard and Jean-Philippe Babeau and Joël Champeau. Model Driven Engineering for Distributed Embedded Real-Time Systems, ISTE, Hermes science and Lavoisier, 2005, 1-905209-32-0
Book sections
inria-00565171v1
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Evaluating Array Expressions on Massively Parallel Machines with Communication/Computation OverlapB. Buchberger and J. Volkert. Parallel Processing: CONPAR 94-VAPP VI, 854, Springer Verlag, pp.713-724, 1994, LNCS
Book sections
inria-00564992v1
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Advances in Design and Specification Languages for SoCs Selected Contributions from FDL'04Pierre Boulet. Kluwer Academic Publishers, pp.303, 2005, 0-387-26149-4. ⟨10.1007/b136935⟩
Books
inria-00585558v1
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N2S3, a Simulator for the Architecture Exploration of Neuromorphic AcceleratorsNeuComp 2015, Mar 2015, Grenoble, France. 2015
Conference poster
hal-01240444v1
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Consommation énergétique des technologies blockchain2021
Other publications
hal-03514983v1
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Outils pour la parallélisation automatiqueGénie logiciel [cs.SE]. Ecole normale supérieure de lyon - ENS LYON, 1996. Français. ⟨NNT : ⟩
Theses
tel-00564899v1
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Contributions aux environnements de programmation pour le calcul intensifGénie logiciel [cs.SE]. Université des Sciences et Technologie de Lille - Lille I, 2002
Habilitation à diriger des recherches
tel-00564904v1
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